This file is written in Verilog to achieve a single cycle processor. It can run in Quartus2.

单周期源文件\adder.v
............\adder4.v
............\alu16.v
............\ALU_control.v
............\control_new.v
............\cpu.bdf
............\cpu.vwf
............\Data_mem.v
............\Ins_mem.v
............\ins_qs.txt
............\Mux32_2.v
............\Mux32_4.v
............\Mux5.v
............\PC.v
............\Registers.v
............\sign_extend.v
............\sign_extend2.v
............\sl2.v
............\sll2.v
单周期源文件

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