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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 148kb
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One exmple of 1602 on board of SPARTAN-3E of xilinx.
Packet file list
(Preview for download)
1602
....\1602.gise
....\1602.ise
....\1602.ntrc_log
....\1602.vhd
....\1602.xise
....\1602_summary.html
....\1602_xdb
....\........\cst.xbcd
....\........\tmp
....\........\...\ise
....\........\...\ise.lock
....\........\...\...\version
....\........\...\...\__OBJSTORE__
....\........\...\...\............\Autonym
....\........\...\...\............\common
....\........\...\...\............\HierarchicalDesign
....\........\...\...\............\..................\HDProject
....\........\...\...\............\..................\.........\HDProject
....\........\...\...\............\..................\.........\HDProject_StrTbl
....\........\...\...\............\..................\__stored_object_table__
....\........\...\...\............\PnAutoRun
....\........\...\...\............\.........\Scripts
....\........\...\...\............\.........\.......\RunOnce_tcl
....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\........\...\...\............\ProjectNavigator
....\........\...\...\............\ProjectNavigator11
....\........\...\...\............\ProjectNavigatorGui
....\........\...\...\............\...................\CViewSelector
....\........\...\...\............\...................\CViewSelector_StrTbl
....\........\...\...\............\...................\File-SynthesisOnly
....\........\...\...\............\...................\File-SynthesisOnly_StrTbl
....\........\...\...\............\...................\Library-SynthesisOnly
....\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
....\........\...\...\............\...................\Process-BehavioralSim-
....\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
....\........\...\...\............\...................\Process-SynthesisOnly-
....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE
....\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VHDL_ARCHITECTURE_StrTbl
....\........\...\...\............\...................\Process-SynthesisOnly-_StrTbl
....\........\...\...\............\...................\Source-BehavioralSim-AutoCompile
....\........\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
....\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile
....\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
....\........\...\...\............\................\dpm_project_main
....\........\...\...\............\................\................\dpm_project_main
....\........\...\...\............\................\................\dpm_project_main_StrTbl
....\........\...\...\............\xreport
....\........\...\...\............\.......\Gc_RvReportViewer-Current-Module
....\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-1602
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-1602_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-LCD1602
....\........\...\...\............\.......\Gc_RvReportViewer-Module-Data-LCD1602_StrTbl
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
....\........\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
....\........\...\...\............\_ProjRepoInternal_
....\........\...\...\__REGISTRY__
....\........\...\...\............\Autonym
....\........\...\...\............\.......\regkeys
....\........\...\...\............\bitgen
....\........\...\...\............\......\regkeys
....\........\...\...\............\bitinit
....\........\...\...\............\.......\regkeys
....\........\...\...\............\common
....\........\...\...\............\......\regkeys
....\........\...\...
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