Using PWM control of LED light off a verilog program development environment quartusII7.0

PWM_LED\.metadata\.lock
.......\.........\.log
.......\.........\.plugins\com.altera.nj.ui\dialog_settings.xml
.......\.........\........\org.eclipse.cdt.core\.log
.......\.........\........\....................\pwm_led.1221969552484.pdom
.......\.........\........\....................\pwm_led_syslib.1221969520984.pdom
.......\.........\........\................ui\dialog_settings.xml
.......\.........\........\.............ore.resources\.history\2f\50967fa69187001d1262abe828d7ef4c
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.......\.........\........\..........................\.projects\pwm_led\.indexes\33\history.index
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.......\.........\........\..........................\.........\.......\.markers
.......\.........\........\..........................\.........\......._syslib\.indexes\33\history.index
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.......\.........\........\..........................\.safetable\org.eclipse.core.resources
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.......\.........\........\............debug.core\.launches\pwm_led Nios II HW configuration.launch
.......\.........\........\..................ui\launchConfigurationHistory.xml
.......\.........\........\............ui.ide\dialog_settings.xml
.......\.........\........\...............workbench\dialog_settings.xml
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.......\.........\version.ini
.......\.sopc_builder\install.ptf
.......\cpu_0.v
.......\cpu_0_bht_ram.mif
.......\cpu_0_dc_tag_ram.mif
.......\cpu_0_ic_tag_ram.mif
.......\cpu_0_jtag_debug_module.v
.......\cpu_0_jtag_debug_module_wrapper.v
.......\cpu_0_mult_cell.v
.......\cpu_0_ociram_default_contents.mif
.......\cpu_0_rf_ram_a.mif
.......\cpu_0_rf_ram_b.mif
.......\cpu_0_test_bench.v
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