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communicationFPGADesign

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 364kb
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  • Author :李****
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contain:matlab and Verilog codes about communication
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无线通信FPGA设计\无线通信FPGA设计[田耘等编著][程序源代码].zip
................\缩略语表.doc
................\matlab代码\matlab\c9\convcode.m
................\..........\......\..\CRCcheck.m
................\..........\......\..\encoderm.m
................\..........\......\..\encode_bit.m
................\..........\......\..\hamming7_4.m
................\..........\......\..\intrlvcode.m
................\..........\......\..\RScode.m
................\..........\......\..\rsc_encode.m
................\..........\......\..\TCMcode.m
................\..........\......\.8\ASKmod.m
................\..........\......\..\F2T.m
................\..........\......\..\LPF.m
................\..........\......\..\MSKmod.m
................\..........\......\..\OFDMmod.m
................\..........\......\..\QAMmod.m
................\..........\......\..\QPSKmod.m
................\..........\......\..\T2F.m
................\..........\......\.7\cicde.m
................\..........\......\..\CICdec.m
................\..........\......\..\cicin.m
................\..........\......\..\CICinterp.m
................\..........\......\..\halfdec.m
................\..........\......\..\halfinterp.m
................\..........\......\..\hbfil.m
................\..........\......\..\multirece.m
................\..........\......\..\multisend.m
................\..........\......\.6\impinvar_bilinear.m
................\..........\......\..\rcosflt_filter.m
................\..........\......\..\rcosine_filter.m
................\..........\......\.13\cell_search_cpich.m
................\..........\......\...\ovsf.m
................\..........\......\...\scramble.m
................\..........\......\...\wcdmasource.m
................\..........\......\..2\correce.m
................\..........\......\...\matchfil.m
................\..........\......\...\rake.m
................\..........\......\..1\adpeq.m
................\..........\......\...\ante.m
................\..........\......\...\FFTlms.m
................\..........\......\...\lms.m
................\..........\......\...\RLS.m
................\..........\......\...\signlms.m
................\..........\......\...\WHT.m
................\..........\......\...\WHTlms.m
................\..........\......\..0\c.mat
................\..........\......\...\costas.m
................\..........\......\...\frame_syn.m
................\..........\......\...\PLLC.m
................\..........\......\...\RRCrece.m
................\..........\......\...\RRCsend.m
................\..........\......\...\symbol_syn.m
................\Verilog代码\readme.txt
................\...........\c9\9-8\rs_enc.v
................\...........\..\..5\crc_16.v
................\...........\..\..2\linearcode.v
................\...........\..\...\lineardecode.v
................\...........\..\..16\tcm_enc.v
................\...........\..\...3\block_ram.xco
................\...........\..\....\interleaver.v
................\...........\..\...1\viterbi.v
................\...........\..\...0\conv_enc.v
................\...........\.8\8-9\fsk_two.v
................\...........\..\..8\two_fsk.v
................\...........\..\..6\QPSK_two.v
................\...........\..\..5\QPSK.v
................\...........\..\..3\ASK_two.v
................\...........\..\..2\two_ASK.v
................\...........\..\..14\ofdm_fft.xco
................\...........\..\....\ofdm_modu.v
................\...........\..\...2\ddsqam.xco
................\...........\..\....\qam16.v
................\...........\..\...0\dds1_cosine.xco
................\...........\..\....\dds1_sine.xco
................\...........\..\....\dds_modu.xco
................\...........\..\....\iqmodu.v
................\...........\..\....\iqsin.v
................\...........\..\....\msk_mult.xco
................\...........\..\....\msk_top.v
................\...........\..\....\s2p.v
................\...........\.7\7-9\crc_interp_2_single.v
................\...........\..\..6\polyfilter.v
................\...........\..\..5\rate4to3.v
................\...........\..\..4\interp
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