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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 83kb
  • Downloaded :0次
  • Author :李****
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
VHDL delay to the start of the function is a simple time delay
Packet file list
(Preview for download)
yanshi\delay.vhd
......\yanshi.qpf
......\yanshi.qsf
......\db\yanshi.db_info
......\..\yanshi.cbx.xml
......\..\yanshi.hif
......\..\yanshi.hier_info
......\..\yanshi.psp
......\..\yanshi.dbp
......\..\yanshi.syn_hier_info
......\..\yanshi.map.qmsg
......\..\yanshi.rtlv_sg.cdb
......\..\yanshi.rtlv.hdb
......\..\yanshi.rtlv_sg_swap.cdb
......\..\yanshi.pre_map.hdb
......\..\yanshi.pre_map.cdb
......\..\yanshi.map.logdb
......\..\yanshi.sgdiff.cdb
......\..\yanshi.sgdiff.hdb
......\..\yanshi.sld_design_entry_dsc.sci
......\..\yanshi.map.cdb
......\..\yanshi.map.hdb
......\..\yanshi.fit.qmsg
......\..\yanshi.cmp.logdb
......\..\yanshi.asm.qmsg
......\..\yanshi.tan.qmsg
......\..\yanshi.cmp.tdb
......\..\yanshi.cmp0.ddb
......\..\yanshi.cmp.cdb
......\..\yanshi.cmp.hdb
......\..\yanshi.cmp.rdb
......\..\yanshi.sim.qmsg
......\..\yanshi.sim.hdb
......\..\yanshi.eds_overflow
......\..\yanshi.sim.vwf
......\..\yanshi.sim.rdb
......\..\wed.zsf
......\..\yanshi.sld_design_entry.sci
......\..\yanshi.eco.cdb
......\yanshi.map.rpt
......\yanshi.flow.rpt
......\yanshi.map.summary
......\yanshi.pin
......\yanshi.fit.rpt
......\yanshi.fit.summary
......\yanshi.pof
......\yanshi.asm.rpt
......\yanshi.tan.summary
......\yanshi.tan.rpt
......\yanshi.done
......\yanshi.vwf
......\yanshi.sim.rpt
......\yanshi.qws
......\db
yanshi
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