Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump correctly. By modelsim simulation, with test code.

microprocessor\adder.v
..............\alu.v
..............\controller.v
..............\datapath.v
..............\datapath.v.bak
..............\datapath1.v
..............\dmem.v
..............\equal.v
..............\flop.v
..............\flop2.v
..............\flopr.v
..............\flopr1.v
..............\flopr3.v
..............\flopr4.v
..............\hazardunit.v
..............\hewenjuan.cr.mti
..............\hewenjuan.mpf
..............\imem.v
..............\memfile.dat
..............\microprocessortest.cr.mti
..............\microprocessortest.mpf
..............\mips.v
..............\mips.v.bak
..............\mux2.v
..............\mux3.v
..............\mux3.v.bak
..............\regfile.v
..............\signext.v
..............\sl2.v
..............\testbench.v
..............\testbench.v.bak
..............\test_flop.v
..............\tes_hazardunit.v
..............\top.v
..............\top.v.bak
..............\transcript
..............\vsim.wlf
..............\work\memfile.dat
..............\....\_info
..............\....\top\verilog.asm
..............\....\...\_primary.dat
..............\....\...\_primary.vhd
..............\....\.est_hazardunit\verilog.asm
..............\....\...............\_primary.dat
..............\....\...............\_primary.vhd
..............\....\.....flop\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\....bench\verilog.asm
..............\....\.........\_primary.dat
..............\....\.........\_primary.vhd
..............\....\sl2\verilog.asm
..............\....\...\_primary.dat
..............\....\...\_primary.vhd
..............\....\.ignext\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\regfile\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\mux3\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\...2\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\.ips\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\.aindec\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\imem\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\hazardunit\verilog.asm
..............\....\..........\_primary.dat
..............\....\..........\_primary.vhd
..............\....\flopr4\verilog.asm
..............\....\......\_primary.dat
..............\....\......\_primary.vhd
..............\....\.....3\verilog.asm
..............\....\......\_primary.dat
..............\....\......\_primary.vhd
..............\....\.....2\verilog.asm
..............\....\......\_primary.dat
..............\....\......\_primary.vhd
..............\....\.....1\verilog.asm
..............\....\......\_primary.dat
..............\....\......\_primary.vhd
..............\....\.....\verilog.asm
..............\....\.....\_primary.dat
..............\....\.....\_primary.vhd
..............\....\....\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\equal\verilog.asm
..............\....\.....\_primary.dat
..............\....\.....\_primary.vhd
..............\....\dmem\verilog.asm

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