VHDL test 1, use of schematic input 4-bit full adder design

experiment1\4f_adder.asm.rpt
...........\4f_adder.bdf
...........\4f_adder.done
...........\4f_adder.fit.rpt
...........\4f_adder.fit.smsg
...........\4f_adder.fit.summary
...........\4f_adder.flow.rpt
...........\4f_adder.jpg
...........\4f_adder.map.rpt
...........\4f_adder.map.summary
...........\4f_adder.pin
...........\4f_adder.pof
...........\4f_adder.qpf
...........\4f_adder.qsf
...........\4f_adder.qws
...........\4f_adder.sim.rpt
...........\4f_adder.sof
...........\4f_adder.tan.rpt
...........\4f_adder.tan.summary
...........\4f_adder.vwf
...........\f_adder.asm.rpt
...........\f_adder.bdf
...........\f_adder.bsf
...........\f_adder.done
...........\f_adder.fit.rpt
...........\f_adder.fit.smsg
...........\f_adder.fit.summary
...........\f_adder.flow.rpt
...........\f_adder.map.rpt
...........\f_adder.map.summary
...........\f_adder.pin
...........\f_adder.pof
...........\f_adder.qpf
...........\f_adder.qsf
...........\f_adder.qws
...........\f_adder.sim.rpt
...........\f_adder.sof
...........\f_adder.tan.rpt
...........\f_adder.tan.summary
...........\f_adder.vwf
...........\h_adder.asm.rpt
...........\h_adder.bdf
...........\h_adder.bsf
...........\h_adder.done
...........\h_adder.fit.rpt
...........\h_adder.fit.smsg
...........\h_adder.fit.summary
...........\h_adder.flow.rpt
...........\h_adder.map.rpt
...........\h_adder.map.summary
...........\h_adder.pin
...........\h_adder.pof
...........\h_adder.qpf
...........\h_adder.qsf
...........\h_adder.qws
...........\h_adder.sof
...........\h_adder.tan.rpt
...........\h_adder.tan.summary
...........\db\4f_adder.asm.qmsg
...........\..\4f_adder.cbx.xml
...........\..\4f_adder.cmp.cdb
...........\..\4f_adder.cmp.hdb
...........\..\4f_adder.cmp.kpt
...........\..\4f_adder.cmp.logdb
...........\..\4f_adder.cmp.rdb
...........\..\4f_adder.cmp.tdb
...........\..\4f_adder.cmp0.ddb
...........\..\4f_adder.dbp
...........\..\4f_adder.db_info
...........\..\4f_adder.eds_overflow
...........\..\4f_adder.fit.qmsg
...........\..\4f_adder.hier_info
...........\..\4f_adder.hif
...........\..\4f_adder.map.cdb
...........\..\4f_adder.map.hdb
...........\..\4f_adder.map.logdb
...........\..\4f_adder.map.qmsg
...........\..\4f_adder.pre_map.cdb
...........\..\4f_adder.pre_map.hdb
...........\..\4f_adder.psp
...........\..\4f_adder.rtlv.hdb
...........\..\4f_adder.rtlv_sg.cdb
...........\..\4f_adder.rtlv_sg_swap.cdb
...........\..\4f_adder.sgdiff.cdb
...........\..\4f_adder.sgdiff.hdb
...........\..\4f_adder.signalprobe.cdb
...........\..\4f_adder.sld_design_entry_dsc.sci
...........\..\4f_adder.sim.qmsg
...........\..\4f_adder.sim.hdb
...........\..\4f_adder.sim.vwf
...........\..\4f_adder.sim.rdb
...........\..\4f_adder.sld_design_entry.sci
...........\..\4f_adder.syn_hier_info
...........\..\4f_adder.tan.qmsg
...........\..\f_adder.asm.qmsg
...........\..\f_adder.cbx.xml
...........\..\f_adder.cmp.cdb
...........\..\f_adder.cmp.hdb
...........\..\f_adder.cmp.kpt
...........\..\f_adder.cmp.logdb

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