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sdram_control

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 2.65mb
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  • Author :李***
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sdram fpag verilog
Packet file list
(Preview for download)
sdram_control\doc\read_me.doc
.............\...\SDRAM.doc
.............\...\sdr_sdram.pdf
.............\doc
.............\sim\altera_mf.v
.............\...\Command.v
.............\...\control_interface.v
.............\...\mt48lc2m32b2.v
.............\...\Params.v
.............\...\sdram_test.cr.mti
.............\...\sdram_test.mpf
.............\...\sdram_test.wlf
.............\...\sdram_test_tb.v
.............\...\transcript
.............\...\vsim.wlf
.............\...\wave.do
.............\...\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
.............\...\....\..........................................\_primary.dat
.............\...\....\..........................................\_primary.vhd
.............\...\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
.............\...\....\.m@f_pll_reg\verilog.asm
.............\...\....\............\_primary.dat
.............\...\....\............\_primary.vhd
.............\...\....\@m@f_pll_reg
.............\...\....\.....ram7x20_syn\verilog.asm
.............\...\....\................\_primary.dat
.............\...\....\................\_primary.vhd
.............\...\....\@m@f_ram7x20_syn
.............\...\....\.....stratixii_pll\verilog.asm
.............\...\....\..................\_primary.dat
.............\...\....\..................\_primary.vhd
.............\...\....\@m@f_stratixii_pll
.............\...\....\............_pll\verilog.asm
.............\...\....\................\_primary.dat
.............\...\....\................\_primary.vhd
.............\...\....\@m@f_stratix_pll
.............\...\....\alt3pram\verilog.asm
.............\...\....\........\_primary.dat
.............\...\....\........\_primary.vhd
.............\...\....\alt3pram
.............\...\....\...accumulate\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\altaccumulate
.............\...\....\...cam\verilog.asm
.............\...\....\......\_primary.dat
.............\...\....\......\_primary.vhd
.............\...\....\altcam
.............\...\....\....dr_rx\verilog.asm
.............\...\....\.........\_primary.dat
.............\...\....\.........\_primary.vhd
.............\...\....\altcdr_rx
.............\...\....\.......tx\verilog.asm
.............\...\....\.........\_primary.dat
.............\...\....\.........\_primary.vhd
.............\...\....\altcdr_tx
.............\...\....\....lklock\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\altclklock
.............\...\....\...ddio_bidir\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\altddio_bidir
.............\...\....\........in\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\altddio_in
.............\...\....\........out\verilog.asm
.............\...\....\...........\_primary.dat
.............\...\....\...........\_primary.vhd
.............\...\....\altddio_out
.............\...\....\....pram\verilog.asm
.............\...\....\........\_primary.dat
.............\...\....\........\_primary.vhd
.............\...\....\altdpram
.............\...\....\...fp_mult\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\altfp_mult
.............\...\....\...lvds_rx\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\altlvds_rx
.............\...\....\........tx\verilog.asm
.............\...\....\..........\_primary.dat
.............\...\....\..........\_primary.vhd
.............\...\....\altlvds_tx
.............\...\....\...mult_accum\verilog.asm
.............\...\....\.............\_primary.dat
.............\...\....\.............\_primary.vhd
.............\...\....\altmult_accum
.............\...\....\.........dd\verilog.asm
.............\...\....\...........\_primary.d
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