In order to incorporate the combined effects of the data size and the process variations on the performance of communication buses, this thesis proposes an extended model for communication synthesis. The proposed model simultaneously performs on-chip communication bus synthesis and voltage scaling under data size and process variations.

1.pdf

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．