ddrct_gen_xp_1_002_1，有关ddr控制的设计程序

ddrct_gen_xp_1_002\default.css
..................\Readme.htm
..................\tutorial
..................\xpga
..................\....\ver1
..................\....\....\eval
..................\....\....\....\Readme.txt
..................\....\....\....\simulation
..................\....\....\....\..........\scripts
..................\....\....\....\..........\.......\eval_runsim_N.do
..................\....\....\....\testbench
..................\....\....\....\.........\ddrct_gen_xp_1_002_params.v
..................\....\....\....\.........\ddr_ddefines.v
..................\....\....\....\.........\ddr_top_tb.v
..................\....\....\....\tests
..................\....\....\....\.....\stimuli_basicrw_cmd_xpga.v
..................\....\....\gui_script
..................\....\....\..........\module_gen.zip
..................\....\....\lib
..................\....\....\...\modelsim
..................\....\....\...\........\ddrct_gen_xp_1_002_lib
..................\....\....\...\........\......................\@a@s_@l@s@b
..................\....\....\...\........\......................\...........\verilog.asm
..................\....\....\...\........\......................\...........\_primary.dat
..................\....\....\...\........\......................\...........\_primary.vhd
..................\....\....\...\........\......................\@b@i_@d@i@r
..................\....\....\...\........\......................\...........\verilog.asm
..................\....\....\...\........\......................\...........\_primary.dat
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..................\....\....\...\........\......................\@b@l@v@d@s@i@n
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..................\....\....\...\........\......................\..............\_primary.dat
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..................\....\....\...\........\......................\@b@l@v@d@s@i@o
..................\....\....\...\........\......................\..............\verilog.asm
..................\....\....\...\........\......................\..............\_primary.dat
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..................\....\....\...\........\......................\@b@l@v@d@s@o@u@t
..................\....\....\...\........\......................\................\verilog.asm
..................\....\....\...\........\......................\................\_primary.dat
..................\....\....\...\........\......................\................\_primary.vhd
..................\....\....\...\........\......................\@b@l@v@d@s@t@r@i
..................\....\....\...\........\......................\................\verilog.asm
..................\....\....\...\........\......................\................\_primary.dat
..................\....\....\...\........\......................\................\_primary.vhd
..................\....\....\...\........\......................\@b@u@f@e@i
..................\....\....\...\........\......................\..........\verilog.asm
..................\....\....\...\........\......................\..........\_primary.dat
..................\....\....\...\........\......................\..........\_primary.vhd
..................\....\....\...\........\......................\@b@u@f@f
..................\....\....\...\........\......................\........\verilog.asm
..................\....\....\...\........\......................\........\_primary.dat
..................\....\....\...\........\......................\........\_primary.vhd
..................\....\....\...\........\......................\@b@u@f@t@h
..................\....\....\...\........\......................\..........\verilog.asm
..................\....\....\...\........\......................\..........\_primary.dat
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