FPGA Vrilog HDL divider input 33MHZ, output 1KHZ-50HZ

clk_div\clk_div.asm.rpt
.......\clk_div.bdf
.......\clk_div.bsf
.......\clk_div.done
.......\clk_div.fit.rpt
.......\clk_div.fit.smsg
.......\clk_div.fit.summary
.......\clk_div.flow.rpt
.......\clk_div.map.rpt
.......\clk_div.map.summary
.......\clk_div.pin
.......\clk_div.pof
.......\clk_div.qpf
.......\clk_div.qsf
.......\clk_div.qws
.......\clk_div.sim.rpt
.......\clk_div.sof
.......\clk_div.tan.rpt
.......\clk_div.tan.summary
.......\clk_div.vwf
.......\.......1000\clk_div1000.asm.rpt
.......\...........\clk_div1000.bsf
.......\...........\clk_div1000.done
.......\...........\clk_div1000.fit.rpt
.......\...........\clk_div1000.fit.smsg
.......\...........\clk_div1000.fit.summary
.......\...........\clk_div1000.flow.rpt
.......\...........\clk_div1000.map.rpt
.......\...........\clk_div1000.map.summary
.......\...........\clk_div1000.pin
.......\...........\clk_div1000.pof
.......\...........\clk_div1000.qpf
.......\...........\clk_div1000.qsf
.......\...........\clk_div1000.qws
.......\...........\clk_div1000.sim.rpt
.......\...........\clk_div1000.sof
.......\...........\clk_div1000.tan.rpt
.......\...........\clk_div1000.tan.summary
.......\...........\clk_div1000.v
.......\...........\clk_div1000.v.bak
.......\...........\clk_div1000.vwf
.......\...........\db\clk_div1000.asm.qmsg
.......\...........\..\clk_div1000.asm.rdb
.......\...........\..\clk_div1000.asm_labs.ddb
.......\...........\..\clk_div1000.cbx.xml
.......\...........\..\clk_div1000.cmp.bpm
.......\...........\..\clk_div1000.cmp.cdb
.......\...........\..\clk_div1000.cmp.ecobp
.......\...........\..\clk_div1000.cmp.hdb
.......\...........\..\clk_div1000.cmp.kpt
.......\...........\..\clk_div1000.cmp.logdb
.......\...........\..\clk_div1000.cmp.rdb
.......\...........\..\clk_div1000.cmp.tdb
.......\...........\..\clk_div1000.cmp0.ddb
.......\...........\..\clk_div1000.cmp_merge.kpt
.......\...........\..\clk_div1000.db_info
.......\...........\..\clk_div1000.eco.cdb
.......\...........\..\clk_div1000.eds_overflow
.......\...........\..\clk_div1000.fit.qmsg
.......\...........\..\clk_div1000.fnsim.hdb
.......\...........\..\clk_div1000.fnsim.qmsg
.......\...........\..\clk_div1000.hier_info
.......\...........\..\clk_div1000.hif
.......\...........\..\clk_div1000.lpc.html
.......\...........\..\clk_div1000.lpc.rdb
.......\...........\..\clk_div1000.lpc.txt
.......\...........\..\clk_div1000.map.bpm
.......\...........\..\clk_div1000.map.cdb
.......\...........\..\clk_div1000.map.ecobp
.......\...........\..\clk_div1000.map.hdb
.......\...........\..\clk_div1000.map.kpt
.......\...........\..\clk_div1000.map.logdb
.......\...........\..\clk_div1000.map.qmsg
.......\...........\..\clk_div1000.map_bb.cdb
.......\...........\..\clk_div1000.map_bb.hdb
.......\...........\..\clk_div1000.map_bb.logdb
.......\...........\..\clk_div1000.pre_map.cdb
.......\...........\..\clk_div1000.pre_map.hdb
.......\...........\..\clk_div1000.rtlv.hdb
.......\...........\..\clk_div1000.rtlv_sg.cdb
.......\...........\..\clk_div1000.rtlv_sg_swap.cdb
.......\...........\..\clk_div1000.sgdiff.cdb
.......\...........\..\clk_div1000.sgdiff.hdb
.......\...........\..\clk_div1000.sim.hdb
.......\...........\..\clk_div1000.sim.qmsg
.......\...........\..\clk_div1000.sim.rdb
.......\...........\..\clk_div1000.simfam
.......\...........\..\clk_div1000.sim_ori.vwf
.......\...........\..\clk_div1000.sld_design_entry.sci
.......\...........\..\clk_div1000.sld_design_entry_dsc.sci
.......\...........\..\clk_div1000.smart_action.txt
.......\...........\..\clk_div1000.syn_hier_info
.......\...........\..\clk_div1000.tan.qmsg
.......\...........\..\clk_div1000.tis_db_list.ddb
.......\...........\..\logic_util_heursitic.dat
.......\...........\..\prev_cmp_clk_div1000.asm.qmsg
.......\...........\..\prev_cmp_clk_div1000.fit.qmsg
.......\...........\..\prev_cmp_clk_div1000.map.qmsg
.......\...........\..\prev_cmp_clk_div1000.qmsg
.......\...........\..\prev_cmp_clk_div1000.sim.qmsg

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