A8255.ZIP contains code that implement a modified 8255 Peripherial Port Controller. The code is written in verilog and project is made for XILINX ISE.

A8255V4
.......\a8255.bgn
.......\a8255.bit
.......\a8255.bld
.......\a8255.cmd_log
.......\a8255.dly
.......\a8255.do
.......\a8255.drc
.......\a8255.lfp
.......\a8255.lso
.......\a8255.mrp
.......\a8255.nc1
.......\a8255.ncd
.......\a8255.ngc
.......\a8255.ngd
.......\a8255.ngm
.......\a8255.ngr
.......\a8255.pad
.......\a8255.pad_txt
.......\a8255.par
.......\a8255.pcf
.......\a8255.placed_ncd_tracker
.......\a8255.prj
.......\a8255.routed_ncd_tracker
.......\a8255.stx
.......\a8255.syr
.......\a8255.twr
.......\a8255.twx
.......\a8255.ucf
.......\a8255.ucf.bak
.......\a8255.ucf.untf
.......\a8255.ut
.......\A8255.V
.......\A8255.V.bak
.......\a8255.xpi
.......\A8255V4.dhp
.......\A8255V4.ise
.......\A8255V4.ise_ISE_Backup
.......\A8255V4.npl.bak
.......\A8255V4_ise6_bak.zip
.......\a8255_last_par.ncd
.......\a8255_map.ncd
.......\a8255_map.ngm
.......\a8255_pad.csv
.......\a8255_pad.txt
.......\a8255_summary.html
.......\a8255_vhdl.prj
.......\automake.log
.......\bitgen.ut
.......\coregen.prj
.......\pio8.v
.......\pio8.v.bak
.......\PROJECT.cr.mti
.......\PROJECT.mpf
.......\testbench.v
.......\testbench.v.bak
.......\transcript
.......\userlang.tpl
.......\vsim.wlf
.......\vsim_stacktrace.vstf
.......\wave.do
.......\work
.......\....\a8255
.......\....\.....\verilog.asm
.......\....\.....\_primary.dat
.......\....\.....\_primary.vhd
.......\....\ctrl8
.......\....\.....\verilog.asm
.......\....\.....\_primary.dat
.......\....\.....\_primary.vhd
.......\....\pio8
.......\....\....\verilog.asm
.......\....\....\_primary.dat
.......\....\....\_primary.vhd
.......\....\simulate_a8255_inout
.......\....\....................\verilog.asm
.......\....\....................\_primary.dat
.......\....\....................\_primary.vhd
.......\....\simulate_inouts
.......\....\...............\verilog.asm
.......\....\...............\_primary.dat
.......\....\...............\_primary.vhd
.......\....\simulate_inputs
.......\....\...............\verilog.asm
.......\....\...............\_primary.dat
.......\....\...............\_primary.vhd
.......\....\simulate_outputs
.......\....\................\verilog.asm
.......\....\................\_primary.dat
.......\....\................\_primary.vhd
.......\....\_info
.......\xst
.......\...\dump.xst
.......\...\........\a8255.prj
.......\...\........\.........\ngx
.......\...\........\.........\...\notopt
.......\...\........\.........\...\opt
.......\...\work
.......\...\....\hdllib.ref
.......\...\....\vlg49

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