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an488_design_example

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  • Update : 2012-11-26
  • Size : 350kb
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FPGA-based LCD display control module
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an488_design_example\code
....................\....\stepmot.v
....................\modelsim
....................\........\stepmot.v
....................\........\stepmot_sim.cr.mti
....................\........\stepmot_sim.mpf
....................\........\test_stepmot.v
....................\........\transcript
....................\........\wave.bmp
....................\........\wave.do
....................\........\work
....................\........\....\@m@a@x@i@i_@p@r@i@m_@d@f@f@e
....................\........\....\............................\verilog.psm
....................\........\....\............................\_primary.dat
....................\........\....\............................\_primary.vhd
....................\........\....\divider
....................\........\....\.......\verilog.psm
....................\........\....\.......\_primary.dat
....................\........\....\.......\_primary.vhd
....................\........\....\divider1
....................\........\....\........\verilog.psm
....................\........\....\........\_primary.dat
....................\........\....\........\_primary.vhd
....................\........\....\maxii_and1
....................\........\....\..........\verilog.psm
....................\........\....\..........\_primary.dat
....................\........\....\..........\_primary.vhd
....................\........\....\maxii_and16
....................\........\....\...........\verilog.psm
....................\........\....\...........\_primary.dat
....................\........\....\...........\_primary.vhd
....................\........\....\maxii_asynch_lcell
....................\........\....\..................\verilog.psm
....................\........\....\..................\_primary.dat
....................\........\....\..................\_primary.vhd
....................\........\....\maxii_b17mux21
....................\........\....\..............\verilog.psm
....................\........\....\..............\_primary.dat
....................\........\....\..............\_primary.vhd
....................\........\....\maxii_b5mux21
....................\........\....\.............\verilog.psm
....................\........\....\.............\_primary.dat
....................\........\....\.............\_primary.vhd
....................\........\....\maxii_bmux21
....................\........\....\............\verilog.psm
....................\........\....\............\_primary.dat
....................\........\....\............\_primary.vhd
....................\........\....\maxii_crcblock
....................\........\....\..............\verilog.psm
....................\........\....\..............\_primary.dat
....................\........\....\..............\_primary.vhd
....................\........\....\maxii_dffe
....................\........\....\..........\verilog.psm
....................\........\....\..........\_primary.dat
....................\........\....\..........\_primary.vhd
....................\........\....\maxii_io
....................\........\....\........\verilog.psm
....................\........\....\........\_primary.dat
....................\........\....\........\_primary.vhd
....................\........\....\maxii_jtag
....................\........\....\..........\verilog.psm
....................\........\....\..........\_primary.dat
....................\........\....\..........\_primary.vhd
....................\........\....\maxii_latch
....................\........\....\...........\verilog.psm
....................\........\....\...........\_primary.dat
....................\........\....\...........\_primary.vhd
....................\........\....\maxii_lcell
....................\........\....\...........\verilog.psm
....................\........\....\...........\_primary.dat
....................\........\....\...........\_primary.vhd
....................\........\....\maxii_lcell_register
....................\........\....\....................\verilog.psm
....................\........\....\....................\_primary.dat
........
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