Write serial port control program with NIIOS, control FPGA and the external D/A, while producing function modulated signals

tiaozhi
.......\.sopc_builder
.......\.............\install.ptf
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.......\.............\preferences.xml
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.......\cpu_jtag_debug_module_sysclk.vhd
.......\cpu_jtag_debug_module_tck.vhd
.......\cpu_jtag_debug_module_wrapper.vhd
.......\cpu_ociram_default_contents.mif
.......\cpu_rf_ram.mif
.......\cpu_test_bench.vhd
.......\db
.......\..\altsyncram_anb1.tdf
.......\..\altsyncram_g602.tdf
.......\..\altsyncram_kh22.tdf
.......\..\altsyncram_qp31.tdf
.......\..\altsyncram_v172.tdf
.......\..\decode_6pa.tdf
.......\..\decode_cpi.tdf
.......\..\mux_3lb.tdf
.......\..\prev_cmp_top.fit.qmsg
.......\..\prev_cmp_top.map.qmsg
.......\..\prev_cmp_top.qmsg
.......\..\top.asm.qmsg
.......\..\top.asm_labs.ddb
.......\..\top.cbx.xml
.......\..\top.cmp.bpm
.......\..\top.cmp.cdb
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.......\..\top.cmp.tdb
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.......\..\top.cmp2.ddb
.......\..\top.db_info
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.......\..\top.pre_map.cdb
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.......\..\top.psp
.......\..\top.root_partition.cmp.atm
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.......\..\top.root_partition.cmp.rcf
.......\..\top.root_partition.map.atm
.......\..\top.root_partition.map.hdbx
.......\..\top.root_partition.map.info
.......\..\top.rtlv.hdb
.......\..\top.rtlv_sg.cdb
.......\..\top.rtlv_sg_swap.cdb
.......\..\top.sgdiff.cdb
.......\..\top.sgdiff.hdb
.......\..\top.signalprobe.cdb
.......\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
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.......\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
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.......\..\top.sld_design_entry.sci
.......\..\top.sld_design_entry_dsc.sci
.......\..\top.syn_hier_info
.......\..\top.tan.qmsg
.......\..\top.tis_db_list.ddb
.......\epcs_controller.vhd
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.......\mode.vhd
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.......\pc1.bsf
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.......\pc1.ptf.pre_generation_ptf
.......\pc1.qip
.......\pc1.sopc
.......\pc1.sopcinfo
.......\pc1.vhd
.......\pc1_generation_script
.......\pc1_log.txt
.......\pc1_setup_quartus.tcl

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