ADI is used to test the communication between the TS201 and the FPGA' s LINK program, compressed file to include VHDL and Verlog code.

link_port-v1.1.0\build\lp_rx\cyclone\lp_rx_top_cyclone.csf
................\.....\.....\.......\lp_rx_top_cyclone.esf
................\.....\.....\.......\lp_rx_top_cyclone.psf
................\.....\.....\.......\lp_rx_top_cyclone.quartus
................\.....\.....\.......\lp_rx_top_cyclone.ssf
................\.....\.....\.......\lp_rx_top_cyclone.v
................\.....\.....\cyclone
................\.....\.....\stratix\lp_rx_top_stratix.csf
................\.....\.....\.......\lp_rx_top_stratix.esf
................\.....\.....\.......\lp_rx_top_stratix.psf
................\.....\.....\.......\lp_rx_top_stratix.quartus
................\.....\.....\.......\lp_rx_top_stratix.ssf
................\.....\.....\.......\lp_rx_top_stratix.v
................\.....\.....\.......\rx_pll.bsf
................\.....\.....\.......\rx_pll.cmp
................\.....\.....\.......\rx_pll.inc
................\.....\.....\.......\rx_pll.v
................\.....\.....\.......\rx_pll_bb.v
................\.....\.....\.......\rx_pll_inst.v
................\.....\.....\stratix
................\.....\lp_rx
................\.....\...tx\cyclone\ddr_clk.v
................\.....\.....\.......\lp_tx_top_cyclone.csf
................\.....\.....\.......\lp_tx_top_cyclone.esf
................\.....\.....\.......\lp_tx_top_cyclone.psf
................\.....\.....\.......\lp_tx_top_cyclone.quartus
................\.....\.....\.......\lp_tx_top_cyclone.ssf
................\.....\.....\.......\lp_tx_top_cyclone.v
................\.....\.....\.......\tx_pll.bsf
................\.....\.....\.......\tx_pll.cmp
................\.....\.....\.......\tx_pll.inc
................\.....\.....\.......\tx_pll.v
................\.....\.....\.......\tx_pll_bb.v
................\.....\.....\.......\tx_pll_inst.v
................\.....\.....\cyclone
................\.....\.....\stratix\ddr_clk.v
................\.....\.....\.......\lp_tx_top_stratix.csf
................\.....\.....\.......\lp_tx_top_stratix.esf
................\.....\.....\.......\lp_tx_top_stratix.psf
................\.....\.....\.......\lp_tx_top_stratix.quartus
................\.....\.....\.......\lp_tx_top_stratix.ssf
................\.....\.....\.......\lp_tx_top_stratix.v
................\.....\.....\.......\tx_pll.bsf
................\.....\.....\.......\tx_pll.cmp
................\.....\.....\.......\tx_pll.inc
................\.....\.....\.......\tx_pll.v
................\.....\.....\.......\tx_pll_bb.v
................\.....\.....\.......\tx_pll_inst.v
................\.....\.....\stratix
................\.....\lp_tx
................\build
................\doc\an332.pdf
................\...\readme.txt
................\doc
................\source\verilog\ddr_clk.v
................\......\.......\link.bdf
................\......\.......\lp_rx.v
................\......\.......\lp_rx.v.bak
................\......\.......\lp_tx.v
................\......\.......\lp_tx.v.bak
................\......\verilog
................\source
................\test\harness\tb\lp_rx.do
................\....\.......\..\lp_rx.mpf
................\....\.......\..\lp_tx.do
................\....\.......\..\lp_tx.mpf
................\....\.......\..\rx_test_harness.v
................\....\.......\..\rx_wave.do
................\....\.......\..\tx_test_harness.v
................\....\.......\..\tx_wave.do
................\....\.......\tb
................\....\harness
................\test
link_port-v1.1.0

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