i2c complete Verilog code is available, including the testbench.

i2c-IPcore\i2c\software\include\oc_i2c_master.h
..........\...\rtl\vhdl\I2C.VHD
..........\...\...\....\i2c_master_bit_ctrl.vhd
..........\...\...\....\i2c_master_byte_ctrl.vhd
..........\...\...\....\i2c_master_top.vhd
..........\...\...\....\readme
..........\...\...\....\tst_ds1621.vhd
..........\...\...\.erilog\i2c_master_bit_ctrl.v
..........\...\...\.......\i2c_master_byte_ctrl.v
..........\...\...\.......\i2c_master_defines.v
..........\...\...\.......\i2c_master_top.v
..........\...\...\.......\timescale.v
..........\...\...\.......\transcript
..........\...\...\.......\i2c\i2c.restore
..........\...\...\.......\...\i2c.ise
..........\...\...\.......\...\i2c_ise9migration.zip
..........\...\...\.......\...\i2c.ise_ISE_Backup
..........\...\...\.......\...\i2c_master_bit_ctrl_summary.html
..........\...\...\.......\...\i2c_master_byte_ctrl_summary.html
..........\...\...\.......\...\i2c_master_top_summary.html
..........\...\doc\i2c_specs.pdf
..........\...\...\src\I2C_specs.doc
..........\...\bench\verilog\i2c_slave_model.v
..........\...\.....\.......\spi_slave_model.v
..........\...\.....\.......\tst_bench_top.v
..........\...\.....\.......\wb_master_model.v
..........\...\.....\.......\transcript
..........\...\.....\.......\CVS\Entries
..........\...\.....\.......\...\Repository
..........\...\.....\.......\...\Root
..........\...\rtl\verilog\i2c\_xmsgs
..........\...\...\.......\...\templates
..........\...\...\.......\i2c
..........\...\bench\verilog\CVS
..........\...\software\include
..........\...\rtl\vhdl
..........\...\...\verilog
..........\...\doc\src
..........\...\bench\verilog
..........\...\software
..........\...\rtl
..........\...\doc
..........\...\bench
..........\i2c
i2c-IPcore

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