This is a work written in VHDL language using state machine control cs5550 for AD conversion code inside that contains the logic analyzer with an analysis of documents. Are highly portable.

cs555
.....\999.stp
.....\AD_CHANGE.bdf
.....\AD_CONTROL.bdf
.....\AD_CONTROL.bsf
.....\AD_CONTROL.ptf
.....\AD_CONTROL.ptf.pre_generation_ptf
.....\AD_CONTROL.qip
.....\AD_CONTROL.sopc
.....\AD_CONTROL.sopcinfo
.....\AD_CONTROL.vhd
.....\AD_CONTROL_generation_script
.....\AD_CONTROL_log.txt
.....\AD_CONTROL_setup_quartus.tcl
.....\AD_CONTROL_sim
.....\..............\atail-f.pl
.....\..............\jtag_uart_input_mutex.dat
.....\..............\jtag_uart_input_stream.dat
.....\..............\jtag_uart_output_stream.dat
.....\..............\uart_input_data_mutex.dat
.....\..............\uart_input_data_stream.dat
.....\..............\uart_log_module.txt
.....\.................\.cdtproject
.....\.................\.project
.....\.................\Newlib C Library
.....\component
.....\.........\freedev_ps2
.....\.........\...........\cb_generator.pl
.....\.........\...........\class.ptf
.....\.........\...........\hdl
.....\.........\...........\...\freedev_ps2.v
.....\.........\...........\...\ps2_keyboard.v
.....\.........\...........\...\ps2_keyboard_interface.v
.....\.........\redlogic_rtl8019
.....\.........\................\cb_generator.pl
.....\.........\................\class.ptf
.....\.........\................\HAL
.....\.........\................\...\inc
.....\.........\................\...\...\redlogic_rtl8019.h
.....\.........\................\...\src
.....\.........\................\...\...\component.mk
.....\.........\................\...\...\Copy of redlogic_rtl8019.c
.....\.........\................\...\...\redlogic_rtl8019_bak.c
.....\.........\................\...\...\redlogic_rtl8019_t.c
.....\.........\................\...\...\spc.exe
.....\.........\................\hdl
.....\.........\................\inc
.....\.........\................\...\redlogic_rtl8019_regs.h
.....\.........\................\UCOSII
.....\.........\................\......\inc
.....\.........\................\......\...\redlogic_rtl8019.h
.....\.........\................\......\src
.....\.........\................\......\...\component.mk
.....\.........\................\......\...\redlogic_rtl8019.c
.....\.........\sram_512x8bit
.....\.........\.............\cb_generator.pl
.....\.........\.............\class.ptf
.....\.........\.............\hdl
.....\cpu.ocp
.....\cpu.sdc
.....\cpu.vhd
.....\cpu_ic_tag_ram.mif
.....\cpu_jtag_debug_module_sysclk.vhd
.....\cpu_jtag_debug_module_tck.vhd
.....\cpu_jtag_debug_module_wrapper.vhd
.....\cpu_mult_cell.vhd
.....\cpu_ociram_default_contents.mif
.....\cpu_rf_ram.mif
.....\cpu_rf_ram_a.mif
.....\cpu_rf_ram_b.mif
.....\cpu_test_bench.vhd
.....\cs5550.asm.rpt
.....\CS5550.bsf
.....\cs5550.cdf
.....\cs5550.done
.....\cs5550.dpf
.....\cs5550.fit.rpt
.....\cs5550.fit.smsg
.....\cs5550.fit.summary
.....\cs5550.flow.rpt
.....\cs5550.jdi
.....\cs5550.map.rpt
.....\cs5550.map.summary
.....\cs5550.pin
.....\cs5550.qpf
.....\cs5550.qsf
.....\cs5550.qws
.....\cs5550.sof
.....\cs5550.sta.rpt
.....\cs5550.sta.summary
.....\cs5550.vhd
.....\cs5550_assignment_defaults.qdf
.....\db
.....\..\altsyncram_3id1.tdf
.....\..\altsyncram_6472.tdf
.....\..\altsyncram_b8p3.tdf
.....\..\altsyncram_cqf1.tdf
.....\..\altsyncram_dqf1.tdf
.....\..\altsyncram_h4g1.tdf
.....\..\altsyncram_i0m1.tdf

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