Verilog HDL programming example explanation example explanation of Verilog HDL programming

Chapter-1
.........\adder
.........\.....\adder.cr.mti
.........\.....\adder.mpf
.........\.....\adder.v
.........\.....\adder_testbench.do
.........\.....\adder_testbench.v
.........\.....\chart





.........\.....\.....\图1-8.bmp
.........\.....\transcript
.........\.....\vsim.wlf
.........\.....\work
.........\.....\....\adder
.........\.....\....\.....\transcript
.........\.....\....\.....\verilog.txt.asm
.........\.....\....\.....\_primary.dat
.........\.....\....\.....\_primary.vhd
.........\.....\....\adder_testbench
.........\.....\....\...............\verilog.asm
.........\.....\....\...............\_primary.dat
.........\.....\....\...............\_primary.vhd
.........\.....\....\_info
Chapter-10
..........\10.2
..........\....\chart




..........\....\csc.cr.mti
..........\....\csc.mpf
..........\....\csc_testbench.v
..........\....\rgb2ycrcb.v
..........\....\transcript
..........\....\vsim.wlf
..........\....\wave


..........\....\work
..........\....\....\csc_testbench
..........\....\....\.............\verilog.asm
..........\....\....\.............\_primary.dat
..........\....\....\.............\_primary.vhd
..........\....\....\rgb2ycrcb
..........\....\....\.........\verilog.asm
..........\....\....\.........\_primary.dat
..........\....\....\.........\_primary.vhd
..........\....\....\_info
..........\10.3
..........\....\chart





..........\....\.....\图10-25.bmp
..........\....\.....\图10-28.bmp
..........\....\.....\表10-3.bmp
..........\....\dct.cr.mti
..........\....\dct.mpf
..........\....\dct.v
..........\....\dctu.v
..........\....\dctub.v
..........\....\dct_cos_table.v
..........\....\dct_mac.v
..........\....\dct_syn.v
..........\....\dct_testbench.v
..........\....\fdct.v
..........\....\qnr.cr.mti
..........\....\timescale.v
..........\....\transcript
..........\....\vsim.wlf
..........\....\wave
..........\....\....\dct.bmp



..........\....\....\fdct.bmp
..........\....\....\zigzag.bmp
..........\....\work
..........\....\....\bench_top
..........\....\....\.........\verilog.asm
..........\....\....\.........\_primary.dat
..........\....\....\.........\_primary.vhd
..........\....\....\dct
..........\....\....\...\verilog.asm
..........\....\....\...\_primary.dat
..........\....\....\...\_primary.vhd
..........\....\....\dctu
..........\....\....\....\verilog.asm
..........\....\....\....\_primary.dat
..........\....\....\....\_primary.vhd
..........\....\....\dctub
..........\....\....\.....\verilog.asm
..........\....\....\.....\_primary.dat

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