Introduction - If you have any usage issues, please Google them yourself
This routine is an independent experiment is designed to allow you familiarize yourself with the basic syntax of VHDL language, which is relatively simple program. To achieve a clock signal clk is the frequency of the function, you can look at the waveform simulation results. Waveform simulation process can refer to video " wave simulation. Exe" file, there is a more detailed method of operation. In fact, routine project already contains a waveform simulation file, we can direct simulation, observe the results.