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Verilog_ADCtestcode

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 142kb
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Introduction - If you have any usage issues, please Google them yourself
the test code for ADC of verilog
Packet file list
(Preview for download)
Verilog控制ADC的全部程序
........................\ADControl
........................\.........\ad_control.bsf
........................\.........\ad_control.v
........................\.........\block1.asm.rpt
........................\.........\block1.bdf
........................\.........\block1.bsf
........................\.........\block1.done
........................\.........\block1.fit.rpt
........................\.........\block1.fit.smsg
........................\.........\block1.fit.summary
........................\.........\block1.flow.rpt
........................\.........\block1.map.rpt
........................\.........\block1.map.summary
........................\.........\block1.pin
........................\.........\block1.qpf
........................\.........\block1.qsf
........................\.........\block1.qws
........................\.........\block1.sim.rpt
........................\.........\block1.tan.rpt
........................\.........\block1.tan.summary
........................\.........\block1.vwf
........................\.........\block1_assignment_defaults.qdf
........................\.........\db
........................\.........\..\add_sub_0fc.tdf
........................\.........\..\add_sub_1fc.tdf
........................\.........\..\add_sub_2fc.tdf
........................\.........\..\add_sub_3dc.tdf
........................\.........\..\add_sub_3fc.tdf
........................\.........\..\add_sub_4dc.tdf
........................\.........\..\add_sub_4fc.tdf
........................\.........\..\add_sub_5dc.tdf
........................\.........\..\add_sub_5fc.tdf
........................\.........\..\add_sub_6dc.tdf
........................\.........\..\add_sub_6fc.tdf
........................\.........\..\add_sub_7dc.tdf
........................\.........\..\add_sub_7fc.tdf
........................\.........\..\add_sub_8dc.tdf
........................\.........\..\add_sub_8fc.tdf
........................\.........\..\add_sub_9dc.tdf
........................\.........\..\add_sub_9fc.tdf
........................\.........\..\add_sub_adc.tdf
........................\.........\..\add_sub_bdc.tdf
........................\.........\..\add_sub_jec.tdf
........................\.........\..\add_sub_kec.tdf
........................\.........\..\add_sub_lec.tdf
........................\.........\..\add_sub_mac.tdf
........................\.........\..\add_sub_mec.tdf
........................\.........\..\add_sub_nec.tdf
........................\.........\..\add_sub_oec.tdf
........................\.........\..\add_sub_pec.tdf
........................\.........\..\add_sub_qec.tdf
........................\.........\..\add_sub_rec.tdf
........................\.........\..\add_sub_sec.tdf
........................\.........\..\add_sub_tec.tdf
........................\.........\..\add_sub_uec.tdf
........................\.........\..\add_sub_vec.tdf
........................\.........\..\alt_u_div_2ue.tdf
........................\.........\..\block1.db_info
........................\.........\..\block1.eco.cdb
........................\.........\..\block1.sim.vwf
........................\.........\..\block1.sld_design_entry.sci
........................\.........\..\lpm_divide_g8m.tdf
........................\.........\..\sign_div_unsign_9nh.tdf
........................\.........\..\wed.wsf
........................\.........\..\wed.zsf
........................\使用说明请参看右侧注释====〉〉.txt
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