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fpganios

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 5.55mb
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  • Author :sca****
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Introduction - If you have any usage issues, please Google them yourself
produced fpga logic analyzer control system nios2 Branch' s own record is absolutely useful papers
Packet file list
(Preview for download)
My_design
.........\cd.vhd
.........\chufakongzhi.bdf
.........\chufakongzhi.bsf
.........\clr.vhd
.........\co.bsf
.........\co.cmp
.........\co.vhd
.........\count.bsf
.........\count.vhd
.........\count2.bsf
.........\count2.vhd
.........\cpu_0.ocp
.........\cpu_0.vhd
.........\cpu_0_ic_tag_ram.mif
.........\cpu_0_jtag_debug_module.vhd
.........\cpu_0_jtag_debug_module_wrapper.vhd
.........\cpu_0_ociram_default_contents.mif
.........\cpu_0_rf_ram.mif
.........\cpu_0_rf_ram_a.mif
.........\cpu_0_rf_ram_b.mif
.........\cpu_0_test_bench.vhd
.........\db
.........\..\altsyncram_80a1.tdf
.........\..\altsyncram_9de1.tdf
.........\..\altsyncram_bde1.tdf
.........\..\altsyncram_f0a1.tdf
.........\..\altsyncram_fd22.tdf
.........\..\altsyncram_fpq.tdf
.........\..\altsyncram_g0a1.tdf
.........\..\altsyncram_i3e1.tdf
.........\..\altsyncram_j3e1.tdf
.........\..\altsyncram_m0a1.tdf
.........\..\altsyncram_qmb1.tdf
.........\..\altsyncram_qt62.tdf
.........\..\altsyncram_stv1.tdf
.........\..\alt_synch_pipe_kc8.tdf
.........\..\alt_synch_pipe_lc8.tdf
.........\..\a_graycounter_np6.tdf
.........\..\a_graycounter_s06.tdf
.........\..\cntr_adh.tdf
.........\..\dcfifo_f8a1.tdf
.........\..\decode_ogi.tdf
.........\..\dffpipe_ed9.tdf
.........\..\dffpipe_fd9.tdf
.........\..\lcd_key_uart.analyze_file.qmsg
.........\..\lcd_key_uart.asm.qmsg
.........\..\lcd_key_uart.cbx.xml
.........\..\lcd_key_uart.cmp.cdb
.........\..\lcd_key_uart.cmp.hdb
.........\..\lcd_key_uart.cmp.kpt
.........\..\lcd_key_uart.cmp.logdb
.........\..\lcd_key_uart.cmp.rdb
.........\..\lcd_key_uart.cmp.tdb
.........\..\lcd_key_uart.cmp0.ddb
.........\..\lcd_key_uart.dbp
.........\..\lcd_key_uart.db_info
.........\..\lcd_key_uart.eco.cdb
.........\..\lcd_key_uart.fit.qmsg
.........\..\lcd_key_uart.hier_info
.........\..\lcd_key_uart.hif
.........\..\lcd_key_uart.map.cdb
.........\..\lcd_key_uart.map.hdb
.........\..\lcd_key_uart.map.logdb
.........\..\lcd_key_uart.map.qmsg
.........\..\lcd_key_uart.pre_map.cdb
.........\..\lcd_key_uart.pre_map.hdb
.........\..\lcd_key_uart.psp
.........\..\lcd_key_uart.pss
.........\..\lcd_key_uart.rtlv.hdb
.........\..\lcd_key_uart.rtlv_sg.cdb
.........\..\lcd_key_uart.rtlv_sg_swap.cdb
.........\..\lcd_key_uart.sgdiff.cdb
.........\..\lcd_key_uart.sgdiff.hdb
.........\..\lcd_key_uart.signalprobe.cdb
.........\..\lcd_key_uart.sld_design_entry.sci
.........\..\lcd_key_uart.sld_design_entry_dsc.sci
.........\..\lcd_key_uart.syn_hier_info
.........\..\lcd_key_uart.tan.qmsg
.........\empty.vhd
.........\EN.vhd
.........\fenpin.bdf
.........\fifo.bsf
.........\fifo.cmp
.........\fifo.vhd
.........\fifo0.bsf
.........\fifo0.cmp
.........\fifo0.vhd

.........\fifo0_waveforms.html

.........\fifo_waveforms.html
.........\full.vhd
.........\hello_led_0
.........\...........\.cdtbuild
.........\...........\.cdtproject
.........\...........\.project
.........\...........\application.stf
.........\...........\Debug
.........\...........\.....\generated_app.sh
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