Verilog prepared with simple arithmetic unit (ALU), can be add, subtract, and, or, exclusive-OR, non-, left, and other functions shifted to right

alu
...\alu.cmd_log
...\alu.ise
...\alu.ise_ISE_Backup
...\alu.lso
...\alu.ngc
...\alu.ngr
...\alu.ntrc_log
...\alu.prj
...\alu.restore
...\alu.stx
...\alu.syr
...\alu.xst
...\alu_summary.html
...\xst
...\...\dump.xst
...\...\........\alu.prj
...\...\........\.......\ngx
...\...\........\.......\...\notopt
...\...\........\.......\...\opt
...\...\........\.......\ntrc.scr
...\...\projnav.tmp
...\...\work
...\...\....\hdllib.ref
...\...\....\vlg0A
...\...\....\.....\alu.bin
...\_xmsgs
...\......\xst.xmsgs

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