E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuits of two modules.

shift_clk
.........\cmp_state.ini
.........\db
.........\..\shift_clk-sim.vwf
.........\..\shift_clk.csf.msg
.........\..\shift_clk.db_info
.........\..\shift_clk.psf.hdb
.........\..\shift_clk.shift_clk.chip.tdb_netlist.EP1S10F780C7.csf.tdb
.........\..\shift_clk.shift_clk.chip.tim_manager.EP1S10F780C7.csf.ddb
.........\..\shift_clk.shift_clk.csf.hdb
.........\..\shift_clk.shift_clk.csf.rdb
.........\..\shift_clk.shift_clk.db_entries.csf.cdb
.........\..\shift_clk.shift_clk.sgate_entries.csf.cdb
.........\..\shift_clk.shift_clk.ssf.hdb
.........\..\shift_clk.shift_clk.ssf.rdb
.........\..\shift_clk.ssf.msg
.........\..\sld_design_entry.ice
.........\Debug.fsf
.........\Release.fsf
.........\serv_req_info.txt
.........\shift_clk.bdf
.........\shift_clk.csf
.........\shift_clk.csf.rpt
.........\shift_clk.eqn
.........\shift_clk.pin
.........\shift_clk.psf
.........\shift_clk.quartus
.........\shift_clk.qws
.........\shift_clk.ssf
.........\shift_clk.ssf.rpt
.........\shift_clk.vwf
.........\shift_pll.bsf
.........\shift_pll.cmp
.........\shift_pll.inc
.........\shift_pll.tdf
.........\shift_pll_inst.tdf

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