FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design

JTAG_UART
.........\cpu.ocp
.........\cpu.v
.........\cpu_ic_tag_ram.mif
.........\cpu_jtag_debug_module.v
.........\cpu_jtag_debug_module_wrapper.v
.........\cpu_ociram_default_contents.mif
.........\cpu_rf_ram_a.mif
.........\cpu_rf_ram_b.mif
.........\cpu_test_bench.v
.........\db
.........\..\altsyncram_9tl1.tdf
.........\..\altsyncram_cub1.tdf
.........\..\altsyncram_e502.tdf
.........\..\altsyncram_ege1.tdf
.........\..\altsyncram_k1l1.tdf
.........\..\altsyncram_l6e1.tdf
.........\..\altsyncram_m6e1.tdf
.........\..\altsyncram_t072.tdf
.........\..\a_dpfifo_8t21.tdf
.........\..\a_fefifo_7cf.tdf
.........\..\cntr_dl8.tdf
.........\..\cntr_p7j.tdf
.........\..\cntr_rj7.tdf
.........\..\decode_aoi.tdf
.........\..\dpram_5h21.tdf
.........\..\nios2_2c5.asm.qmsg
.........\..\nios2_2c5.asm_labs.ddb
.........\..\nios2_2c5.cbx.xml
.........\..\nios2_2c5.cmp.cdb
.........\..\nios2_2c5.cmp.hdb
.........\..\nios2_2c5.cmp.kpt
.........\..\nios2_2c5.cmp.logdb
.........\..\nios2_2c5.cmp.rdb
.........\..\nios2_2c5.cmp.tdb
.........\..\nios2_2c5.cmp0.ddb
.........\..\nios2_2c5.cmp2.ddb
.........\..\nios2_2c5.dbp
.........\..\nios2_2c5.db_info
.........\..\nios2_2c5.eco.cdb
.........\..\nios2_2c5.fit.qmsg
.........\..\nios2_2c5.hier_info
.........\..\nios2_2c5.hif
.........\..\nios2_2c5.map.cdb
.........\..\nios2_2c5.map.hdb
.........\..\nios2_2c5.map.logdb
.........\..\nios2_2c5.map.qmsg
.........\..\nios2_2c5.pre_map.cdb
.........\..\nios2_2c5.pre_map.hdb
.........\..\nios2_2c5.psp
.........\..\nios2_2c5.rtlv.hdb
.........\..\nios2_2c5.rtlv_sg.cdb
.........\..\nios2_2c5.rtlv_sg_swap.cdb
.........\..\nios2_2c5.sgdiff.cdb
.........\..\nios2_2c5.sgdiff.hdb
.........\..\nios2_2c5.signalprobe.cdb
.........\..\nios2_2c5.sld_design_entry.sci
.........\..\nios2_2c5.sld_design_entry_dsc.sci
.........\..\nios2_2c5.smp_dump.txt
.........\..\nios2_2c5.syn_hier_info
.........\..\nios2_2c5.tan.qmsg
.........\..\scfifo_1n21.tdf
.........\delay.bdf
.........\delay.bsf
.........\delay_counter.bsf
.........\delay_counter.v
.........\delay_counter_bb.v
.........\jtag_uart
.........\.........\.cdtbuild
.........\.........\.cdtproject
.........\.........\.project
.........\.........\application.stf
.........\.........\Debug
.........\.........\.....\generated_app.sh
.........\.........\.....\jtag_uart.elf
.........\.........\.....\makefile
.........\.........\.....\obj
.........\.........\.....\...\hello_led.d
.........\.........\.....\...\hello_led.o
.........\.........\.....\subdir.mk
.........\.........\hello_led.c
.........\.........\readme.txt
.........\jtag_uart.v
.........\jtag_uart_1
.........\...........\.cdtbuild
.........\...........\.cdtproject
.........\...........\.project
.........\...........\application.stf
.........\...........\Debug
.........\...........\.....\generated_app.sh
.........\...........\.....\jtag_uart_1.elf
.........\...........\.....\makefile
.........\...........\.....\obj
.........\...........\.....\...\hello_led.d
.........\...........\.....\...\hello_led.o
.........\...........\.....\subdir.mk
.........\...........\hello_led.c
.........\...........\readme.txt
.........\jtag_uart_1_syslib
.........\..................\.cdtbuild

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