VHDL-FPGA-Verilog List Page 984

VHDL-FPGA-Verilog list

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PLL_success Downloaded：1: Digital PLL, Manchester generation and decoding, verilog hdl
Date : 2025-08-07 Size : 7.43mb User : www
fifo Downloaded：0: FIFO buffer design and VHDL testbench code
Date : 2025-08-07 Size : 1.71mb User : 叶宗英
counters Downloaded：0: A 255 counter of VHDL，for Beginners Reference
Date : 2025-08-07 Size : 1kb User : 叶宗英
conditioner Downloaded：0: VHDL design of air-conditioning systems finite state automata with VHDL testbench code
Date : 2025-08-07 Size : 1kb User : 叶宗英
FIR-filter Downloaded：0: VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
Date : 2025-08-07 Size : 8kb User : 叶宗英
RAMexio Downloaded：0: verilog language, PWM speed control test procedures fresh Ladder
Date : 2025-08-07 Size : 1kb User : hehh
idt723641 Downloaded：0: VERILOG Twill the IDT dual-port RAM drive good use
Date : 2025-08-07 Size : 14kb User : hehh
PID-controller Downloaded：0: PID controller designed with VHDL,with VHDL testbench code.
Date : 2025-08-07 Size : 2kb User : 叶宗英
divider Downloaded：0: Multiple frequency divider with VHDL testbench code
Date : 2025-08-07 Size : 1kb User : 叶宗英
MCU_to_FPGA Downloaded：0: FPGA and MCU communication code, the preparation of VHDL has been verified
Date : 2025-08-07 Size : 1kb User : 曾宪深
lcd_12864 Downloaded：0: lcd12864 with the Chinese character display program, using the state machine ways, has been verified
Date : 2025-08-07 Size : 2kb User : 曾宪深
Frequency_8bit Downloaded：0: 8 FPGA-based digital frequency meter, after I verified, the error is very small, the results through the digital display (complete works)
Date : 2025-08-07 Size : 845kb User : 曾宪深

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