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VHDL-FPGA-Verilog list
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iq_balance
Downloaded:0
Iq amplitude imbalance adjustment module can be resolved carrier and sideband leakage problems.
Date
: 2025-07-30
Size
: 7kb
User
:
chan
socket_apps
Downloaded:0
socket programming routines to achieve in the xilinx sdk environment, easy to understand, can be used as a reference design
Date
: 2025-07-30
Size
: 34kb
User
:
chan
verilog
Downloaded:0
verilog courseware, details about the languages and applications designed for FPgA have a good effect
Date
: 2025-07-30
Size
: 25.56mb
User
:
刘利
aadd4
Downloaded:0
lookahead adder verilog description, faster, can be integrated
Date
: 2025-07-30
Size
: 153kb
User
:
peyo
adsub4
Downloaded:0
verilog written on subtraction can be integrated faster
Date
: 2025-07-30
Size
: 176kb
User
:
peyo
alu
Downloaded:0
verilog prepared by the ALU unit can be integrated with non-executable plus or minus five kinds of computing
Date
: 2025-07-30
Size
: 354kb
User
:
peyo
src
Downloaded:0
32-bit adder, verilog HDL
Date
: 2025-07-30
Size
: 3kb
User
:
ginlee
QuartusII12.0-
Downloaded:0
This file is installed and used QuartusII12.0 tutorials, including installation guides and create a document processes.
Date
: 2025-07-30
Size
: 4.55mb
User
:
zhaozhongxiao
12864
Downloaded:0
Can be achieved, 12864 shows simple Chinese characters. Suitable for beginners to learn and study.
Date
: 2025-07-30
Size
: 1kb
User
:
kuang
Light-water
Downloaded:0
Light water
Date
: 2025-07-30
Size
: 276kb
User
:
pudn
s_machine
Downloaded:0
Single process Moore state machine, st0 to st4 five conversion between different states. Good performance of synchronous sequential logic module Compared with other VHDL description method, the state machine to diverse V
Date
: 2025-07-30
Size
: 331kb
User
:
杜雨峰
coder83
Downloaded:0
8-3 priority encoder module, based on VHDL din0- din7 eight binary input encoded output three coding results. Adopt positive logic design, high level effectively.
Date
: 2025-07-30
Size
: 321kb
User
:
杜雨峰
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