VHDL-FPGA-Verilog List Page 713

VHDL-FPGA-Verilog list

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i2c_code Downloaded：0: I2C protocol which as been verified and tested using testbench
Date : 2025-06-29 Size : 26kb User : hr
viterbideoderupdated Downloaded：0: Viterbi decoder source code is in verilog with CRCv
Date : 2025-06-29 Size : 2kb User : hr
Encrypt_Decrypt(DES)_Verilog Downloaded：0: Encrypt and decrypt DES algorithm in verilog
Date : 2025-06-29 Size : 8kb User : hr
picture_vga Downloaded：0: VGA interface program design based on FPGA (little green men run)
Date : 2025-06-29 Size : 3.63mb User : 常云鹏
uart_rx_module24 Downloaded：0: UART serial interface communication based on FPGA, this modular by receiving PC serial port data (8), converted into parallel 24 data output
Date : 2025-06-29 Size : 13.21mb User : 常云鹏
DDS Downloaded：0: Module based on FPGA DDS waveform，Adjustable frequency phase
Date : 2025-06-29 Size : 115kb User : 常云鹏
led0 Downloaded：0: One of the most simple LED the experimental program, for newcomers to learn and reference, easy to understand
Date : 2025-06-29 Size : 3.15mb User : 常云鹏
spi Downloaded：0: Spi communication module based on FPGA (16 bit data output)
Date : 2025-06-29 Size : 7.72mb User : 常云鹏
LM75-TTT Downloaded：0: VHDL realization of LM75 LM75 controller read data
Date : 2025-06-29 Size : 1kb User : 向东
fp1-40-1_1 Downloaded：0: fpga any frequency output accuracy " = 2 , serial control division factor, from 50hz-51.2k precision divider, which also includes the decimal point processing. Communication part: baud processing module, data accepta
Date : 2025-06-29 Size : 6.79mb User : houjiajun
delay Downloaded：0: VHDL code, source with the phase difference between the two DDS, can now be used to produce 1m phase programmable clock accuracy can be accurate to 0.01 points. Output two clocks with start control bit
Date : 2025-06-29 Size : 1kb User : houjiajun
irigb_quartusii Downloaded：0: irigb code, quartus ii b code implementations, automatic code generation b.
Date : 2025-06-29 Size : 238kb User : houjiajun

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