VHDL-FPGA-Verilog List Page 601

VHDL-FPGA-Verilog list

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7_07_DCMSim Downloaded：0: xilinx demo code
Date : 2025-06-24 Size : 1.37mb User : 钱学文
DIVIDER Downloaded：0: verilog code for divider verilog code for dividerverilog code for divider
Date : 2025-06-24 Size : 2kb User : HP
nrf Downloaded：0: nrf24l01 and fpga
Date : 2025-06-24 Size : 5.62mb User : 王崎
shuzizhonganjian Downloaded：0: Design a digital clock, this design requires a 12 or 24 hexadecimal hexadecimal have the hours, minutes, seconds, chronograph function digital clock, and can be adjusted hours and minutes.
Date : 2025-06-24 Size : 650kb User : bian
ma_slice_temp Downloaded：0: verilog code temp h
Date : 2025-06-24 Size : 1kb User : Ethanhao
lab4 Downloaded：0: to realize keyboard funtion
Date : 2025-06-24 Size : 410kb User : wjt
meimei Downloaded：0: Electronic clock that can display time, date, sports stopwatch, alarm
Date : 2025-06-24 Size : 2.12mb User : krist
final-project Downloaded：0: final project- design processor
Date : 2025-06-24 Size : 2kb User : duyphan
Architecture-for-Dataflow-Graphs-with-Feedback.ra Downloaded：0: Architecture for Dataflow Graphs with Feedback
Date : 2025-06-24 Size : 297kb User : duyphan
VHDL_-position-control Downloaded：0: This program written in VHDL language of stepper motor positioning control program
Date : 2025-06-24 Size : 5kb User : 王强
hdl-master Downloaded：0: AD9361' s ip nuclear, debugging has been passed on vivado can run through. AD9361 is a dual-channel transceiver convenient, usually used in 3G/4G base stations.
Date : 2025-06-24 Size : 1.26mb User : liufei
LCD-control-VHDL-program Downloaded：0: These programs can help people learn VHDL language better understanding of VHDL, and how to use the program to control the LED.
Date : 2025-06-24 Size : 10kb User : 桂婷

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