VHDL-FPGA-Verilog List Page 589

VHDL-FPGA-Verilog list

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vga Downloaded：0: VGA with Verilog HDL code written, breadboard verified.
Date : 2025-06-23 Size : 2kb User : Daniel
sram_test Downloaded：0: Written using Verilog SRAM test program, which Xianxiang SRAM write data, and then read out the data for comparison.
Date : 2025-06-23 Size : 1kb User : Daniel
flash Downloaded：0: Written using Verilog FLASH test program. Xianxiang FLASH write data inside, and then read out the data for comparison.
Date : 2025-06-23 Size : 1kb User : Daniel
IIR Downloaded：0: Achieve an IIR filter with Verilog and simulation in ISE inside.
Date : 2025-06-23 Size : 1kb User : Daniel
SDRAM Downloaded：0: Written using Verilog SDRAM test program. Xianxiang SDRAM write data inside, and then read out the data for comparison.
Date : 2025-06-23 Size : 8kb User : Daniel
advconfig Downloaded：0: In the Xilinx Zynq development board, ADV chip through the IIC configuration.
Date : 2025-06-23 Size : 105kb User : ycfh1ss
DULE-RAM Downloaded：0: Based on dual port ram VERILOG example, the relatively simple, not very complicated, entry understand it.
Date : 2025-06-23 Size : 99kb User : 张是非
project Downloaded：0: Nanjing subway station， based on the beginning and the end station, automatic calculation of fares.
Date : 2025-06-23 Size : 147kb User : 王苏
clock18div Downloaded：0: Clock Divider, divfactor of 18
Date : 2025-06-23 Size : 1kb User : Huy
Digital_Filter_FPGA Downloaded：0: Digital Filter in VHDL
Date : 2025-06-23 Size : 1kb User : Huy
SR_SerIn Downloaded：0: Shift Register, Serial In Parallel Out VHDL
Date : 2025-06-23 Size : 1kb User : Huy
Testbench_SR_SerIn Downloaded：0: Testbench for Shift Register, Serial in Parallel out
Date : 2025-06-23 Size : 7kb User : Huy

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