VHDL-FPGA-Verilog List Page 521

VHDL-FPGA-Verilog list

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dual_priority_encoder2 Downloaded：0: this is a combination circuit,Implement the eight priority encoder，
Date : 2025-06-20 Size : 1.19mb User : liting
DATA_SEND1 Downloaded：0: vhdl code for w300 and I doenload @ chines site
Date : 2025-06-20 Size : 4kb User : saeidbarati
eetop.cn_dds Downloaded：0: the DDS design based on verilog
Date : 2025-06-20 Size : 3.02mb User : 王亮
0714 Downloaded：0: This is a simple VHDL based program for beginners to write a rich electronic clock.
Date : 2025-06-20 Size : 565kb User : zyn
DC-Adder_Array Downloaded：0: 1) requires the use of fast carry chain (Look Ahead) design a 21-bit adder 2) the use of structured design methods, all adders are used in step 1) 21-bit adder 3) was added in the adder array pipeline structure (Pipelinc
Date : 2025-06-20 Size : 7kb User : 李少博
AsynCFIFO Downloaded：0: Cross clock domains and asynchronous FIFO, use the pointer to move, do not move the data, eliminating cross clock domain signal through a two-stage competition latch
Date : 2025-06-20 Size : 2kb User : 李少博
phone Downloaded：0: Implemented by DE0 board telephone billing, basic function: to set the call mode, you can initiate credit balance, toggle switch into the talk mode, and deduct the cost of a call based on call time and the corresponding
Date : 2025-06-20 Size : 3.99mb User : 张三
sinewave-case Downloaded：0: Use verilog language and case statement to achieve sinusoidal waveform, and use modelsim complete waveform simulation.
Date : 2025-06-20 Size : 64kb User : 刘云
dierci Downloaded：0: M sequence 2011 CEC signal generator generates e title 10kbit/s - 100Kbit/s, and a pseudo-random sequence
Date : 2025-06-20 Size : 8.01mb User : 张宏达
AD9854_VHD Downloaded：0: Debug FPGA-based AD9854 can produce the highest frequency waveform 120M
Date : 2025-06-20 Size : 96kb User : 李肖遥
ADC0809 Downloaded：0: ADC0809 chip analog to digital conversion and the value displayed on the common cathode LED
Date : 2025-06-20 Size : 549kb User : LCY
DM9000A Downloaded：0: DM9000A FPGA interface for NIOS timescope
Date : 2025-06-20 Size : 16kb User : 白杨

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