VHDL-FPGA-Verilog List Page 461

VHDL-FPGA-Verilog list

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Tetris-VHDL Downloaded：0: Using FPGA and VGA monitor to develop a Tetris game. Developed using VHDL language and Xilinx .
Date : 2025-06-18 Size : 3.79mb User : 彭铭仕
xulie Downloaded：0: Sequence detection, after detecting a sequence of 11010 lighting, files are written with verilog
Date : 2025-06-18 Size : 344kb User : 夏冬青
spi_verilog Downloaded：0: In more details: 1. The master pulls SSEL down to indicate to the slave that communication is starting (SSEL is active low). 2. The master toggles the clock eight times and sends eight data bits on its MOSI line. At the
Date : 2025-06-18 Size : 8kb User : michael
CNT4 Downloaded：0: Quaternary adding counter
Date : 2025-06-18 Size : 165kb User : 曾
Buffer Downloaded：0: parametrizable register and mux in VHDL of data rage, using std_logic_vector type
Date : 2025-06-18 Size : 2kb User : Felipe
wgsph_lab Downloaded：0: DDFS Verilog DDFS Verilog DDFS Verilog DDFS Verilog
Date : 2025-06-18 Size : 1kb User : Mohit
ETH_SRC Downloaded：0: ethernet Verilog
Date : 2025-06-18 Size : 1.2mb User : 王长友
LVDS_SRC Downloaded：0: lvds Verilog 512 frame
Date : 2025-06-18 Size : 434kb User : 王长友
uart_control Downloaded：0: uart contrl Verilog
Date : 2025-06-18 Size : 1kb User : 王长友
rxd_interface Downloaded：0: Verilog uart rxdinterface
Date : 2025-06-18 Size : 1kb User : 王长友
txd_control Downloaded：0: uart TXD——contrl Verilog
Date : 2025-06-18 Size : 1kb User : 王长友
rxd_control Downloaded：0: uart rxd contrl Verilog
Date : 2025-06-18 Size : 1kb User : 王长友

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