VHDL-FPGA-Verilog List Page 442

VHDL-FPGA-Verilog list

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URAT_VHDL_CODE_TEST_OK Downloaded：0: URAT VHDL program _ with _ test correctly
Date : 2025-06-17 Size : 2kb User : 于工
ASK_DEMODULATION_AND_TEST_CODE Downloaded：0: ASK demodulation VHDL procedures and simulation, the project has been used, easy to use
Date : 2025-06-17 Size : 1kb User : 于工
ASK_modulation_code Downloaded：0: ASK modulation VHDL program, easy to use, has been tested
Date : 2025-06-17 Size : 1kb User : 于工
CPSK_modulation_code Downloaded：0: CPSK modulation VHDL procedures, the test is correct, has been used
Date : 2025-06-17 Size : 1kb User : 于工
ex1_clkdiv Downloaded：0: This experiment can be said to be the most basic experiments verilog entry, and we do not do a lot of theoretical analysis, practice is the last word. When the CPLD' s I/O (FM) is low, the transistor is turned on, the
Date : 2025-06-17 Size : 492kb User : 贺亚晨
ex2_key Downloaded：0: The experiment needs to implement a simple three buttons control the three LEDs light or dark control. For example, button 1 controls the light emitting diode 1. On initial power light emitting diode 1 does not shine, wh
Date : 2025-06-17 Size : 299kb User : 贺亚晨
ex3_johnson Downloaded：0: The so-called Johnson counters, in fact, plainly nothing more than a little water lamp complex experiments. Water lights add a button control, open and close and change direction light water under the control of the keys
Date : 2025-06-17 Size : 136kb User : 贺亚晨
ex4_seg7 Downloaded：0: 7-segment (not counting the decimal point) is also very simple principle, it is nothing more than the seven light-emitting diodes. This seven light-emitting diodes have a common terminal, must be connected to GND (common
Date : 2025-06-17 Size : 143kb User : 贺亚晨
ex5_mux Downloaded：0: The multiplier is the number of a digital system in the basic module. From the principle that it belongs to the combinational logic category but the actual engineering design, it tends to use methods to implement sequent
Date : 2025-06-17 Size : 425kb User : 贺亚晨
askisi Downloaded：0: Simple vhdl code example
Date : 2025-06-17 Size : 3kb User : Avgeris Thanasis
tanchishe Downloaded：0: VHDL Snake
Date : 2025-06-17 Size : 3kb User : ken
DS18B20 Downloaded：0: Date : 2025-06-17 Size : 210kb User : 田春东

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