VHDL-FPGA-Verilog List Page 424

VHDL-FPGA-Verilog list

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clkdivverilog Downloaded：0: clkdiv using verilog，
Date : 2025-12-30 Size : 57kb User : sui
dds Downloaded：0: Generate sine wave, direct digital frequency synthesis method of square wave, sawtooth wave, triangle wave and other basic waveform.
Date : 2025-12-30 Size : 1kb User : marui
encoder-based-on-Gray-code Downloaded：0: Design of VHDL encoder based on Gray code, can be run directly in the chamber
Date : 2025-12-30 Size : 63kb User : 漆广文
xapp592 Downloaded：1: SDI sending and receiving procedures, the use of XILINX nuclear IP
Date : 2025-12-30 Size : 1.6mb User : 周占民
quadratic_func_latest.tar Downloaded：0: QUADRATIC_FUNC used to implement arctan
Date : 2025-12-30 Size : 350kb User : jack abraham
ALU32 Downloaded：0: 32 bit ALU RTL Code using VHDL
Date : 2025-12-30 Size : 369kb User : prasanth
Risc128 Downloaded：0: 128 bit RISC processor implementation in verilog
Date : 2025-12-30 Size : 409kb User : prasanth
beep Downloaded：0: Buzzer alarm sound experiment drop. . drop. .
Date : 2025-12-30 Size : 131kb User : 王鸿雪
Clk50M_div_1HZ Downloaded：0: Crossover experiment, 50M clock divider is 1HZ, output LED1, shiny
Date : 2025-12-30 Size : 152kb User : 王鸿雪
dled Downloaded：0: Dynamic digital display experiment
Date : 2025-12-30 Size : 184kb User : 王鸿雪
key_led Downloaded：0: Read key signal experiment If you press the key1, then lit LED1 If you press the key2, then lit LED1-LED2 So, if the next press key8, then all lights 8 led
Date : 2025-12-30 Size : 122kb User : 王鸿雪
tlc549adc Downloaded：0: Using the state machine to achieve the TLC549 sampling control, adjustable experiments (in the lower left corner of the development board backplane) potentiometer RW1, change ADC Analog input value, after the data acquis
Date : 2025-12-30 Size : 224kb User : 王鸿雪

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