VHDL-FPGA-Verilog List Page 4231

VHDL-FPGA-Verilog list

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lpt03 Downloaded：0: This is 8255 in the design, so I do not know whether the hope of gaining certification
Date : 2025-05-16 Size : 272kb User : runclever
gongchengsheji-477 Downloaded：0: logmap algorithm based on the achievement of VHDL. The communication system log-map algorithm to achieve the number of VHDL
Date : 2025-05-16 Size : 21kb User : 李超
gongcehngsheji_477-2 Downloaded：0: use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Date : 2025-05-16 Size : 6kb User : 李超
chuzuchejifeixitong Downloaded：1: taxi system of billing, physical verification. Simple procedures.
Date : 2025-05-16 Size : 6kb User : 李超
VHDL3 Downloaded：0: This is a vending machine in VHDL source code, the game had been sown topic, for your reference.
Date : 2025-05-16 Size : 522kb User :
temcon Downloaded：0: this procedure was used assembly language and applicable to the Series 51 microcontroller, the procedures detailed footnotes.
Date : 2025-05-16 Size : 5kb User : 胡建兵
xljcq Downloaded：0: sequence generator on the Verilog. Hope you can help.
Date : 2025-05-16 Size : 3kb User : 曹杨
serial_communication Downloaded：0: source code, the code used veilog HDL language, and after I repeatedly verified.
Date : 2025-05-16 Size : 3kb User : 徐燕玲
Booth_Multiplier Downloaded：0: Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Date : 2025-05-16 Size : 1kb User : 韓堇
frame_sync Downloaded：1: frame synchronization module Veriolog source. The ModelSim of a project. A test document.
Date : 2025-05-16 Size : 24kb User : 刘仪
hamin0132 Downloaded：0: series guitar code modules, using Verilog languages, as Modelsim of a project.
Date : 2025-05-16 Size : 31kb User : 刘仪
QPSK2154 Downloaded：1: QPSK VERLOG source of the MODELSIM of a project, test vector.
Date : 2025-05-16 Size : 23kb User : 刘仪

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