VHDL-FPGA-Verilog List Page 4182

VHDL-FPGA-Verilog list

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AsynCommCtrl Downloaded：0: VHDL-based serial asynchronous communication circuit design, including serial transmitter, asynchronous receiver. and controller vhdl
Date : 2025-05-18 Size : 4kb User : 飘来的南风
xiyiji Downloaded：0: washing machine controller, including cleaning, bleaching water, dehydration state, vhdl
Date : 2025-05-18 Size : 4kb User : 飘来的南风
i2c_7111_7128 Downloaded：0: vhdl, and the i2c control philips 7111 and 7128
Date : 2025-05-18 Size : 8kb User : kevin
fpga_spi Downloaded：0: document contains useful fpga achieve isp Interface source, as well as the processor interface, testing is ARM7 processor.
Date : 2025-05-18 Size : 2.06mb User : 张创贞
FPGA_SONGER Downloaded：1: FPGA-based hardware music concert circuit design to achieve a complete VHDL code. and a detailed account of how the PDF download and set up the jumper, and "Butterfly" in a series of development platforms GW48 download d
Date : 2025-05-18 Size : 729kb User : wyy
FPGA_TENNIS Downloaded：0: FPGA-based table tennis game hardware circuit design and realization of a complete VHDL code. and a detailed account of how the PDF download and jumper settings and in a series of development platforms GW48 download debu
Date : 2025-05-18 Size : 304kb User : wyy
VHDL-ysw Downloaded：0: CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time- and-switch K1 phase mi
Date : 2025-05-18 Size : 2kb User : 杨仕伟
CUS_SPI-VHDL Downloaded：0: this as VHDL code SPI communication, all in a compressed package, please read carefully before use.
Date : 2025-05-18 Size : 4kb User : 藏瑞
ug_fifo Downloaded：0: be integrated FIFO memory, all in a compressed package, tested, can be used.
Date : 2025-05-18 Size : 496kb User : 藏瑞
CRC-Verilog Downloaded：0: this Cyclic Redundancy is well-tested Verilog code for a variety of criteria, such as CYXLIC REDUNDANCY
Date : 2025-05-18 Size : 3kb User : 藏瑞
samll Downloaded：0: This is a group of small Verilog code procedures for the use of novice practitioners.
Date : 2025-05-18 Size : 9kb User : 藏瑞
DE2_D5M Downloaded：0: In Quartus ii 10.0 Read Bayer format from D5M camera and convert to RGB format, through SDRAM, output on VGA port.
Date : 2025-05-18 Size : 209kb User : Aaron

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