VHDL-FPGA-Verilog List Page 398

VHDL-FPGA-Verilog list

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keyscanverilog Downloaded：0: Based on the DE2-70 development board of four key KEY0- KEY3 test procedures, can control the direction of the entertaining diversions and run
Date : 2025-06-13 Size : 411kb User : 吉泽
LED_seg7 Downloaded：0: Based on the DE2-70 development board eight buttons seven segment digital tube detection procedures, can be controlled digital refresh pipe 0 f 16 characters
Date : 2025-06-13 Size : 362kb User : 吉泽
mux16 Downloaded：0: Based on the DE2-70 development board 16 x 16 multiplier, easy to understand
Date : 2025-06-13 Size : 851kb User : 吉泽
uartverilog Downloaded：0: Based on the DE2-70 development board single-byte serial port to send and receive data procedures, procedures simple, test available
Date : 2025-06-13 Size : 474kb User : 吉泽
verilogvga Downloaded：0: Based on the DE2-70 development board VGA interface implementation procedures, can be displayed on a VGA screen images of the 800* 600 resolution, refresh rate of 60 hz
Date : 2025-06-13 Size : 7.49mb User : 吉泽
taximeter-in-verilog Downloaded：0: This procedure is for the taximeter FPGA simulation functions implemented using verilog language. You can see description of the specific function in the rar package.
Date : 2025-06-13 Size : 267kb User : 巨好人一枚
shuzijifenfa Downloaded：0: Digital integration of EDA linear and circular interpolation algorithm
Date : 2025-06-13 Size : 442kb User : 苏大
dac7512 Downloaded：0: Implement A/D conversion，Given input, observe the output voltage, VHDL program.
Date : 2025-06-13 Size : 473kb User : 李炎
Sorted Downloaded：0: Buck converter and supply power and gain to its range
Date : 2025-06-13 Size : 3.65mb User : InayathullaKhan
vending-machine-project Downloaded：0: vending machine VHDL FPGA Altera
Date : 2025-06-13 Size : 677kb User : Ipan
calculator-project-VHDL-FPGA Downloaded：0: Calculator PROJECT FPGA ALTERA DE-2
Date : 2025-06-13 Size : 1.46mb User : Ipan
10_rom_test Downloaded：0: rom test
Date : 2025-06-13 Size : 5mb User : zhouhaimin

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