VHDL-FPGA-Verilog List Page 3941

VHDL-FPGA-Verilog list

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sdram Downloaded：0: sdram test controller altera
Date : 2025-06-08 Size : 1.45mb User : yangchun
huawei_logic_Design Downloaded：0: FPGA logic design, vhdl/verilog altera/xilinx Introduction
Date : 2025-06-08 Size : 1.95mb User : zhang
Vhdl Downloaded：0: VHDL can be faster and better understanding of the entry there are a large number of examples of analysis
Date : 2025-06-08 Size : 178kb User : www
shu_zi_zhong Downloaded：0: This procedure introduces VHDL digital clock with the wording, in the hope that useful to everybody
Date : 2025-06-08 Size : 3kb User : 薛永华
suoxianghuan Downloaded：0: Phase-Locked Loop Simulation as well as containing text, hoping to have help. Phase-locked loop of communication is very important
Date : 2025-06-08 Size : 685kb User : 蔡立凤
onehehe Downloaded：0: Verilog design Cymometer 4, can be measured square wave, triangle wave, sine wave measuring range 10Hz ~ 10MHz, measurement resolution of 1Hz, the measurement error 1 Hz measurement channel sensitivity 50mV
Date : 2025-06-08 Size : 374kb User : oywj
iic_bus_example Downloaded：0: Use VHDL to build the IIC bus, corresponding with the FPGA hardware development platform
Date : 2025-06-08 Size : 212kb User : 惠普
camera.tar Downloaded：1: Camera
Date : 2025-06-08 Size : 407kb User : 惠普
bluetooth Downloaded：0: ip nuclear, Bluetooth bluetooth realize the FPGA hardware
Date : 2025-06-08 Size : 16kb User : 惠普
video_compression_systems.tar Downloaded：0: Nuclear ip video compression for FPGA system development
Date : 2025-06-08 Size : 182kb User : 惠普
usb11.tar Downloaded：0: FPGA
Date : 2025-06-08 Size : 360kb User : 惠普
DE2_Default Downloaded：0: DE2 development board based on the VGA display module, for your reference
Date : 2025-06-08 Size : 263kb User : lq

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