VHDL-FPGA-Verilog List Page 3877

VHDL-FPGA-Verilog list

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8-bit Downloaded：0: VHDL basic computing, the use of 8bit for the multiplier, will be the value of two strings of 8bit input multiplied after
Date : 2025-06-10 Size : 1kb User : 王小居
shuzizhong Downloaded：0: The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hour
Date : 2025-06-10 Size : 416kb User : 盼盼
Verilog--shiyanbaogao Downloaded：0: The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have cond
Date : 2025-06-10 Size : 15kb User : 盼盼
DS1307_LCD Downloaded：0: Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
Date : 2025-06-10 Size : 1.25mb User : iversn
I2CController Downloaded：0: Xilinx
Date : 2025-06-10 Size : 22kb User : iversn
CycloneIII_SB_3C25 Downloaded：0: Altera
Date : 2025-06-10 Size : 1.41mb User : iversn
VDHL Downloaded：0: Elevator designed to control the lift design 6 original VHDL language
Date : 2025-06-10 Size : 159kb User : tdh
jsq Downloaded：0: This procedure for 24-hour timer, stable error-free. Easy-to-use, is the Verilog HDL language beginners guide.
Date : 2025-06-10 Size : 1kb User :
eda Downloaded：0: Based on EDA technology design four decimal system solutions Cymometer
Date : 2025-06-10 Size : 104kb User : 小草
0ds7cINj Downloaded：0: Digital Cymometer VHDL procedures and simulation of the file name: plj.vhd.- Function: frequency meter. With four shows that will automatically count seven decimal results, automatic selection of effective data- four for
Date : 2025-06-10 Size : 98kb User : 小草
cnt Downloaded：0: Both a relatively good counter VHDL code: one is the generic n-bit counter, one is the syntax used in the more comprehensive. Is a better learning materials
Date : 2025-06-10 Size : 1kb User : 郭新稳
VGA-VerilogHDL Downloaded：0: Verilog HDL prepared with VGA display driver
Date : 2025-06-10 Size : 138kb User : liping

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