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fpga-plus
Downloaded:0
FPGA on the slide, very useful to explain. Mainly related to fpga-plus kinds of knowledge.
Date
: 2025-06-13
Size
: 1.17mb
User
:
xiao yu
alu
Downloaded:0
Use VHDL to achieve the eight kinds of computing ALU, hairtail unsigned addition and subtraction, multiplication and division, with or XOR and seek anti-
Date
: 2025-06-13
Size
: 1kb
User
:
helen
a
Downloaded:0
ADPLL of high level phase locked loop
Date
: 2025-06-13
Size
: 1.4mb
User
:
bc
rs232_rec5
Downloaded:0
Date
: 2025-06-13
Size
: 529kb
User
:
111
Downloaded:0
51 Single-chip design of the electronic code lock
Date
: 2025-06-13
Size
: 11kb
User
:
张明明
pll
Downloaded:0
Collection of digital phase-locked loop design articles related articles. Mainly VHDL design languages.
Date
: 2025-06-13
Size
: 9.61mb
User
:
gk
USB
Downloaded:0
USB source code, based on the VHDL language, verified in QuartusII above its function
Date
: 2025-06-13
Size
: 5kb
User
:
周
divider
Downloaded:0
The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value of N is set up the corresponding figure
Date
: 2025-06-13
Size
: 1kb
User
:
Tomy Lee
DDR_SDRAM_controller
Downloaded:0
ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Date
: 2025-06-13
Size
: 998kb
User
:
shroy
dianji
Downloaded:0
QuartusII environment, for the three-phase experimental board upds shot six motor
Date
: 2025-06-13
Size
: 1kb
User
:
陈晨
XilinxisdisclosingthisSpecification
Downloaded:0
Xilinx is disclosing this Specification? Chapter 1
Date
: 2025-06-13
Size
: 654kb
User
:
xujj
FSCQ1565RP
Downloaded:0
FSCQ1565RPJ TAG-driven algorithm is MCU to configure the FPGA model J TAG key. Algorithm called SVF profile, to explain the syntax specification to generate a strict TAP bus timing, driver MCU generic I/O pin to complete
Date
: 2025-06-13
Size
: 1.09mb
User
:
xujj
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