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VHDL-FPGA-Verilog list
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MyProject
Downloaded:0
3-8 decoder simulation. Selected in this experiment simulation software is MAX+ Plus II Version 9.3, schematic source files stored in the MyProject directory for 138decoder.gdf, otherwise I write experimental reports, Ha
Date
: 2025-12-30
Size
: 219kb
User
:
zhang
FPGAdesignrule
Downloaded:0
A very good script, hope that we do so, huh, huh.
Date
: 2025-12-30
Size
: 903kb
User
:
liujakie
an501_design_example
Downloaded:0
PWM files for CPLD, learn how to write VHDL language program
Date
: 2025-12-30
Size
: 279kb
User
:
xiaox
fir_16
Downloaded:0
fir filter-verilog, the fir filter based on the Verilog source code
Date
: 2025-12-30
Size
: 725kb
User
:
zhc
cymometer
Downloaded:0
VerilogHDL languages using digital frequency meter
Date
: 2025-12-30
Size
: 830kb
User
:
cherry
FIR_VHDL
Downloaded:0
FIR filter VHDL code can modify the impact of the value function
Date
: 2025-12-30
Size
: 1kb
User
:
李扬
LOCK
Downloaded:0
FPGA-based electronic password by design, detailed design and some code
Date
: 2025-12-30
Size
: 220kb
User
:
李扬
VHDLjiaotongdeng
Downloaded:0
Traffic lights on the graduation project of VHDL design, including source code and simulation procedures related to the report graphics.
Date
: 2025-12-30
Size
: 1.49mb
User
:
乐乐
DDR_SDRAM_controller
Downloaded:0
DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Date
: 2025-12-30
Size
: 129kb
User
:
xbl
16bit_FFT
Downloaded:0
16:00 FFT of the VHDL source code, including detailed design documents.
Date
: 2025-12-30
Size
: 683kb
User
:
xbl
jia
Downloaded:0
2FSK modulation function, welcomed the download. You re welcome a
Date
: 2025-12-30
Size
: 601kb
User
:
jiji
4bit_buma_adder
Downloaded:0
Verilog operation: the source code to write their own input, complementary code output by the state machine to control the four adder, in order to ensure timing, adder module ahead of the last bit adder, including test b
Date
: 2025-12-30
Size
: 2kb
User
:
wizard
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