VHDL-FPGA-Verilog List Page 3844

VHDL-FPGA-Verilog list

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eth_ocm_80_2 Downloaded：0: ethernet wishbone interface
Date : 2025-06-16 Size : 204kb User : esl
ata.tar Downloaded：0: PowerFull ATA Host Controller
Date : 2025-06-16 Size : 816kb User : esl
ApbGPIO Downloaded：0: PowerFull Apb GPIO Controller
Date : 2025-06-16 Size : 1kb User : esl
ApbTimer Downloaded：0: PowerFull Apb Timer Controller
Date : 2025-06-16 Size : 3kb User : esl
core3DES Downloaded：0: Full Des Simulation Code
Date : 2025-06-16 Size : 1.8mb User : esl
CoreAES128 Downloaded：0: Full AES Simulation Code
Date : 2025-06-16 Size : 1.28mb User : esl
ahbapb Downloaded：2: AMBA2.0 standard AHB2APb Bridge, through the verification code
Date : 2025-06-16 Size : 4kb User : LIANG
ModelSim_License Downloaded：2: Altera Modesim cracked version of the LICENCE. Decompress after download: 1. Direct running mentorkg.exe (generated copy license.txt to the D: altera80modelsim_ae the next copy of this directory or mentorkg.exe run) .2.
Date : 2025-06-16 Size : 306kb User : xingyu
IPOFPIC Downloaded：0: SCM pic source code, based on this IP core can modify MCU peripherals, and on this basis to develop their own single-chip microcomputer.
Date : 2025-06-16 Size : 39kb User : luzhao
project_01_Booth_Algorithm Downloaded：0: Booth Algorithm is a relatively simple figure has multiplied its way, that is, using bit scan mode, skip to 00,11 by fast
Date : 2025-06-16 Size : 96kb User : xoso
i2c Downloaded：0: A state machine by VHDL language I2C source code
Date : 2025-06-16 Size : 3kb User : 蔡飞
USB Downloaded：0: Use VHDL to achieve USB IP core, we can refer to the following
Date : 2025-06-16 Size : 1.09mb User : 蔡飞

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