VHDL-FPGA-Verilog List Page 3816

VHDL-FPGA-Verilog list

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VHDL Downloaded：0: State machine and the VHDL design, described in detail the basic structure of state machines, function and classification, as well as finite state machine of the general design ideas and methods, state machine to select
Date : 2025-06-17 Size : 71kb User : 史东寒
zj Downloaded：0: VHDL programming, shift register, 8, support the left, shifted to right
Date : 2025-06-17 Size : 11kb User : wangjun
zj Downloaded：0: VHDL Programming shifter left and right moving mobile
Date : 2025-06-17 Size : 1kb User : wangjun
j Downloaded：0: VHDL programming shift register. The left and shifted to right
Date : 2025-06-17 Size : 1.98mb User : wangjun
zj Downloaded：1: VHDL programming shift register. The left and shifted to right
Date : 2025-06-17 Size : 3kb User : wangjun
FPGA_jiaocheng_yu_shiyan Downloaded：0: The most important thing is seven from simple to complex experiments, including: the basis of the experimental basis for a _FPGA_LED experiment II _seg7 the basis of experiment and simulation experiments based on three e
Date : 2025-06-17 Size : 5.78mb User : yuezhiying_007
liucengdianti Downloaded：0: Six-storey elevator controller: You can basically realize the six-storey elevator controller functions.
Date : 2025-06-17 Size : 5kb User : 孙超
vhdl_clock Downloaded：0: VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function
Date : 2025-06-17 Size : 7kb User : 孙超
2-QUARTUSII Downloaded：0: Let us be more understanding of EDA technology in daily life importance.
Date : 2025-06-17 Size : 549kb User : 马剑
multiplyingunit Downloaded：0: Its multiplier principle is: the sum of multiplication through each shift principle to achieve, from the lowest bit multiplicand to start, if 1, then the multiplier on the left after the first and add if for 0, the left
Date : 2025-06-17 Size : 134kb User : 张华
sin125 Downloaded：0: Using FPGA to achieve DDS signal generator (sine wave 125kHz)
Date : 2025-06-17 Size : 192kb User : 杜海明
serial Downloaded：0: VHDL-based serial communication based on VHDL Serial Communication
Date : 2025-06-17 Size : 369kb User : 戴明

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