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Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication
Date : 2025-06-19 Size : 6kb User : eldis

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Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section
Date : 2025-06-19 Size : 7kb User : eldis

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Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer
Date : 2025-06-19 Size : 561kb User : eldis

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MCPU is a minimal cpu aimed to fit into a 32 Macrocell CPLD- one of the smallest available programmable logic devices. While this CPU is not powerful enough for real world applications it has proven itself as a valuable
Date : 2025-06-19 Size : 243kb User : eldis

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Uart verilog code
Date : 2025-06-19 Size : 15kb User : shenhao

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the stopwatch based on fpga written with vhdl
Date : 2025-06-19 Size : 1kb User : youngbing

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USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
Date : 2025-06-19 Size : 1kb User : Somasekhar

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USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
Date : 2025-06-19 Size : 1kb User : Somasekhar

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USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
Date : 2025-06-19 Size : 2kb User : Somasekhar

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USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
Date : 2025-06-19 Size : 1kb User : Somasekhar

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HDB3 codec realize, with the practical application of c expression is not strong, only to illustrate the principle.
Date : 2025-06-19 Size : 188kb User : lixingjian

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Introduce how to read and write the Flash using Nios II[SOPC、Nios II、DE2]
Date : 2025-06-19 Size : 1.05mb User : bobgeng
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