VHDL-FPGA-Verilog List Page 3760

VHDL-FPGA-Verilog list

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dianzizhong Downloaded：0: Clock Electronics Design and Simulation, VHDL language
Date : 2025-06-20 Size : 58kb User : DAVID
diantikongzhi Downloaded：0: Elevator controller design and simulation verification, VHDL language
Date : 2025-06-20 Size : 159kb User : DAVID
unicntr Downloaded：0: General registers, can be bi-directional counting storage, mode of data through the three-bit control
Date : 2025-06-20 Size : 1kb User : 份基金
verilog_tech Downloaded：0: This article describes the development of Verilog HDL language and its history, the primary capacity. And explain in detail the various use.
Date : 2025-06-20 Size : 11.93mb User : 陈建
mini-uart Downloaded：0: Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Date : 2025-06-20 Size : 248kb User : serein
UART Downloaded：0: UART simple state machine to prepare, as a curriculum design information, suitable for entry-
Date : 2025-06-20 Size : 574kb User : 李欣
Pads-HotKey-Editor Downloaded：0: hardware PCB Pads-HotKey-Editor
Date : 2025-06-20 Size : 31kb User : jangyongwon
Electronicorgan Downloaded：0: Electronic organ prepared using VHDL generator to perform a simple circuit Papers
Date : 2025-06-20 Size : 1.17mb User : lijing
UseofFPGA Downloaded：0: Use of FPGA implementation of the DDS, sine wave output, output frequency adjustable
Date : 2025-06-20 Size : 458kb User : 徐晓
usb11 Downloaded：0: Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Date : 2025-06-20 Size : 405kb User : 戴求淼
can Downloaded：0: Based on Verilog HDL a CAN bus IP core.
Date : 2025-06-20 Size : 87kb User : 戴求淼
yinpinxinhaofenxiyi Downloaded：0: VHDL-based audio signal analyzer, an electronic design competition first prize
Date : 2025-06-20 Size : 4.94mb User : 杨天

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