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VHDL-FPGA-Verilog list
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PCMencoder
Downloaded:0
According to the characteristics of PCM coding,here we use VHDL to design a editing device。
Date
: 2025-06-20
Size
: 94kb
User
:
大海
DE2_USB_API
Downloaded:0
This is ALTERA' s DE2 Development Board regarding the USB API to develop examples of
Date
: 2025-06-20
Size
: 1.32mb
User
:
翁文天
lcd_demo
Downloaded:0
colored LED
Date
: 2025-06-20
Size
: 1kb
User
:
wxq1989
FPGAPLLdesign
Downloaded:0
FPGA+PLLdesign and practice
Date
: 2025-06-20
Size
: 4kb
User
:
wxq1989
KX_7Cprogramstatement
Downloaded:0
KX-7C statement of FPGA lab
Date
: 2025-06-20
Size
: 872kb
User
:
wxq1989
lcdfinal
Downloaded:0
LCD display,verilog,quartusII
Date
: 2025-06-20
Size
: 499kb
User
:
amy
2008.09-scripts_only
Downloaded:0
reference script of synopsys icc
Date
: 2025-06-20
Size
: 82kb
User
:
steven
FPGA_Code_and_training_materials
Downloaded:0
Compressed packet contains: FPGA design of the primary classes and training classes improve classroom PPT experiment' s source code experimental guide book!
Date
: 2025-06-20
Size
: 42.71mb
User
:
hehuilong
mdio-md
Downloaded:1
At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA completed by the MII management
Date
: 2025-06-20
Size
: 2kb
User
:
leon
clktest
Downloaded:0
In the development process, usually the reliability of the test clock, there are phase changes, the duty cycle changes. Implementation of the code phase of the clock change and the duty cycle changes.
Date
: 2025-06-20
Size
: 1kb
User
:
leon
nios_small
Downloaded:0
The smallest example for Nios II
Date
: 2025-06-20
Size
: 3.51mb
User
:
xiejun
barrel_shifter
Downloaded:0
VHDL implementation of a barrel—shifter, able to achieve at one clock cycle of data (0-12 bit) Arithmetic Shift Right
Date
: 2025-06-20
Size
: 1kb
User
:
过时无双
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