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VHDL-FPGA-Verilog list
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A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Date : 2025-06-20 Size : 10kb User : TTJ

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A 32-bit floating-point multipliers, can be two format IEEE 754 values multiplied
Date : 2025-06-20 Size : 2kb User : TTJ

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Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division
Date : 2025-06-20 Size : 18kb User : TTJ

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This is a complete nuclear pwm ip can be instantiated in SOPC in the nuclear, you can download, and absolutely so.
Date : 2025-06-20 Size : 18kb User : lizhiqiang

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16-bit fixed-point FFT-DSP implementation of the FPGA (the relevant codes and instructions)
Date : 2025-06-20 Size : 3.57mb User : tanghongwu

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test bench for spi communication
Date : 2025-06-20 Size : 1kb User : Onur

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FPGA development of frequently used sub-frequency, sub-frequency is easy, but the program can achieve arbitrary duty cycle of arbitrary frequency, using Verilog prepared, very easy to use.
Date : 2025-06-20 Size : 1kb User : 小泉儿

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altera DE2 own default testing procedures to test all devices
Date : 2025-06-20 Size : 4kb User : chxinrui

Very good Xilinx FPGA technology advanced
Date : 2025-06-20 Size : 1.63mb User : 陈成

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A Design of the A/D Convertion Sampling Control Module Based on FPGA
Date : 2025-06-20 Size : 204kb User : sunlei

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For the FPGA of the SOPC ip nuclear, IPCore study are a good encoding tutorial
Date : 2025-06-20 Size : 50kb User : 滕骞

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ethernet files verilog code
Date : 2025-06-20 Size : 4kb User : minh
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