VHDL-FPGA-Verilog List Page 3709

VHDL-FPGA-Verilog list

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4646413214 Downloaded：0: NiosII with 32-bit processors to achieve RS232 communication, can give a reference for beginners.
Date : 2025-06-22 Size : 766kb User : 王磊
8832135 Downloaded：0: A " percentage of seconds, seconds, minutes," digital stopwatch timer can be achieved within an hour of precision to the hundredth of a second time. Digital stopwatch readers can display the digital display throu
Date : 2025-06-22 Size : 43kb User : 王磊
60seconds Downloaded：0: 60 seconds stopwatch design, may be suspended and the sub-count
Date : 2025-06-22 Size : 326kb User : 刘三平
code Downloaded：0: Some programs more concern please .........
Date : 2025-06-22 Size : 296kb User : 林
datapath_fifo Downloaded：0: datapath_fifo used in DMA contect PCI in the DAB system the format of this file is VHDL
Date : 2025-06-22 Size : 1kb User : hjy
cnt10 Downloaded：0: decimal adder vhdl counter the success of design debugging
Date : 2025-06-22 Size : 27kb User : 程诗宇
cordic Downloaded：0: cordic implementation in vhdl&c
Date : 2025-06-22 Size : 11kb User : sim
yuv_rgb Downloaded：0: Complete video streaming ITUR656 standard data format to RGB conversion. Test module
Date : 2025-06-22 Size : 2kb User : 黄涛
sel_stamp Downloaded：0: Money function can be realized stamp vending machine, to buy two stamps, one dollar and the Pentagon
Date : 2025-06-22 Size : 1kb User : 黄涛
fadder Downloaded：0: The use of two and a half adder to form the full adder is a simple entry-vhdl language
Date : 2025-06-22 Size : 1kb User : rosebud
VGA_Ctrl Downloaded：0: Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to write a response to Avalon from the CPU ports of the control sig
Date : 2025-06-22 Size : 1kb User : 黄涛
key Downloaded：0: KEY SCAN VHDL
Date : 2025-06-22 Size : 148kb User : weibao

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