VHDL-FPGA-Verilog List Page 3642

VHDL-FPGA-Verilog list

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ppx16 Downloaded：0: Vhdl code of ppx16 series MCU core, and includes the realization of two MCU- P16C55 and P16F84 according to this core
Date : 2025-06-24 Size : 52kb User : 卢刚
web_cpu88 Downloaded：0: Realization of intel microprocessor 8088 in VHDL language, and can be tested and simulated with ModelSim.
Date : 2025-06-24 Size : 590kb User : 卢刚
main_dct Downloaded：0: verilog code for dct
Date : 2025-06-24 Size : 2kb User : dheeru
i80386 Downloaded：1: Vhdl simulation of intel s 80386 microprocessor, is valuable for reference
Date : 2025-06-24 Size : 8kb User : 卢刚
VHDL Downloaded：0: 8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
Date : 2025-06-24 Size : 1kb User : lijinling
fft_fpga Downloaded：0: Wrote it myself on the development of fpga module fft.
Date : 2025-06-24 Size : 150kb User : 巴音
vaa Downloaded：0: (1) to design a metric four of its frequency range 1Hz ~ 9.999KHz 6 N3 G8 k (U-@ ' n* A (2) After the counting process, preserve and display the results
Date : 2025-06-24 Size : 1kb User : lijinling
router_routing Downloaded：0: NOC-chip networks realized fpga-based, routing module.
Date : 2025-06-24 Size : 1kb User : 巴音
uart_my Downloaded：0: Serial verilog design code, ran in the fpga, correct the problem.
Date : 2025-06-24 Size : 2kb User : 巴音
router_fifo Downloaded：0: Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
Date : 2025-06-24 Size : 1kb User : 巴音
pwm__vhdl Downloaded：0: Vhdl language-based pulse width modulation. And two pulse output
Date : 2025-06-24 Size : 883kb User : 邹细男
router_fifo Downloaded：0: Himself wrote a piece on the network routing node of the fifo module, the work frequency of 1ghz.
Date : 2025-06-24 Size : 1kb User : 巴音

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