VHDL-FPGA-Verilog List Page 3624

VHDL-FPGA-Verilog list

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lab1 Downloaded：0: lab1 report, with codelab1 report, with code
Date : 2025-11-07 Size : 323kb User : rui@rui.com
sopcniosexample Downloaded：0: Sopc through the quartusII to build a simple system nios, nios there is also a simple example of the steps in detail
Date : 2025-11-07 Size : 1.13mb User : maylag_1
seven_segment Downloaded：0: Paragraph written by veirlog display can display the metric system into the above paragraph shows that the number of
Date : 2025-11-07 Size : 2kb User : Truman, Chien
state_machine_design Downloaded：0: This is a state machine on the information, which Moore and Miller explained the design of state machine instances, and there are examples of very detailed.
Date : 2025-11-07 Size : 471kb User : maylag_1
ad_conv Downloaded：0: CPLD to control the use of AD to voltage sampling, and sampling the value of output
Date : 2025-11-07 Size : 1kb User : 帅
voltage_measure Downloaded：0: The use of CPLD measurement range of the input signal, save value
Date : 2025-11-07 Size : 1kb User : 帅
dig_scan Downloaded：0: The AD sample into the eight-bit decimal numerical size, and dynamic display with digital control
Date : 2025-11-07 Size : 1kb User : 帅
loopdisp Downloaded：0: CPLD to control the use of six LED dynamic display to display the numerical
Date : 2025-11-07 Size : 1kb User : 帅
VHDL Downloaded：0: VHDL for FPGA study
Date : 2025-11-07 Size : 27kb User : renlei
QPSK Downloaded：2: for ofdm system
Date : 2025-11-07 Size : 1kb User : 周美红
dianziqin Downloaded：0: The design of realization eight sound electronic organses, and supplementary auto broadcast function
Date : 2025-11-07 Size : 2kb User : renyucai
led Downloaded：0: led
Date : 2025-11-07 Size : 1kb User : yu

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