VHDL-FPGA-Verilog List Page 3605

VHDL-FPGA-Verilog list

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alu Downloaded：0: adder base on FPGA ，verilog HDL
Date : 2025-06-26 Size : 1kb User : lijiaming
sms4 Downloaded：0: This is a hardware algorithm sms4 language, the language used is VHDL.
Date : 2025-06-26 Size : 68kb User : 藤叶
pwm1_register_fil Downloaded：0: PWM
Date : 2025-06-26 Size : 1kb User : 谢明
VHDL_introduction Downloaded：0: VHDL programming,more abstract and more practical.
Date : 2025-06-26 Size : 457kb User : liulinzhong
maichong2 Downloaded：0: pulse generator,good choice.
Date : 2025-06-26 Size : 1kb User : 吴次仁
fd32_c Downloaded：0: latch，32bits.
Date : 2025-06-26 Size : 1kb User : 吴次仁
gain_ctl Downloaded：0: gain controller
Date : 2025-06-26 Size : 1kb User : 吴次仁
div_2m_to_2 Downloaded：0: 2MHz to 2Hz divider
Date : 2025-06-26 Size : 1kb User : 吴次仁
mux2_1 Downloaded：0: mux2 to 1
Date : 2025-06-26 Size : 1kb User : 吴次仁
jiAOTONGDENG Downloaded：1: Simulation of this experiment is located at the crossroads of major traffic lights, traffic lights at the crossroads of divided into two horizontal and vertical direction, each direction of traffic lights are above the r
Date : 2025-06-26 Size : 1kb User : 耳水山
clk Downloaded：0: Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules.
Date : 2025-06-26 Size : 500kb User : kg21kg
CLK_V Downloaded：0: Quartus II project files, is a typical FPGA-based digital clock project, there are sub-50MHz frequency, counting, decoding modules. The use of Verilog language.
Date : 2025-06-26 Size : 584kb User : kg21kg

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